A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

A test apparatus is provided for use with a mainframe and an adapter. The test apparatus includes a logical adapter interface unit and a control system. The logical adapter interface unit is interposable between the adapter and the mainframe whereby an I/O signal transmittable from the adapter and to the mainframe is transmitted through the logical adapter interface unit. The logical adapter interface unit is configured to manipulate the I/O signal. The control system is coupled to the logical adapter interface unit and the mainframe and is configured to control manipulations of the I/O signal by the logical adapter interface unit to mimic a condition of I/O traffic being run through the adapter and to log a response of the mainframe to the manipulations.

Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.

A system of monitoring performance of an electronic device including: a plurality of performance monitoring circuits included in an electronic device, wherein the plurality of performance monitoring circuits are configured to generate a plurality of monitor output signals including performance data of the electronic device; a monitoring bus configured to receive the plurality of monitor output signals and generate a. bus output signal by interleaving the performance data included in the plurality of monitor output signals; and an embedded trace router configured to receive the bus output signal and store, in a memory device included in the electronic device, the performance data. included in the bus output signal,

An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

An I/O control circuit includes a plurality of IO cells including an input section for stimulating a plurality of (n) pins of a device under test (DUT) and an output section for processing data output by the pins. The input section of each cell includes a latched driver each including a driver input, a first driver output, a next state driver output, and a current source. The next state driver output and current source are for coupling to drive the pins, and the latched drivers are serially connected with the first driver output of an earlier IO cell connected to the driver input of a next IO cell. The output section of each cell includes an analog to digital converter (ADC) for coupling to the n pins, and a memory element coupled to an output of the ADC.

Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.

Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.