Adjustable integrated circuits and methods for designing the same are provided. In one embodiment, a method of designing an integrated circuit includes determining a plurality of design criteria of the integrated circuit; designing a plurality of circuit blocks of the integrated circuit in accordance with the plurality of design criteria, where one or more circuit blocks in the plurality of circuit blocks include one or more feedback paths; designing a circuit performance monitor, where the circuit performance monitor includes one or more replica feedback paths corresponding to the one or more feedback paths in the one or more circuit blocks, and where the circuit performance monitor is configured to monitor feedback path information of the one or more replica feedback paths; verifying the plurality of circuit blocks and the circuit performance monitor to meet the plurality of design criteria; and producing a verified description of the integrated circuit for manufacturing.

A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance c.sub.n of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance c.sub.p of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

A method and an apparatus for reducing the effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values c.sub.n of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value c.sub.mean of the measured performance values c.sub.n, as an approximation of an ideal performance value c.sub.0, selecting one performance value c.sub.j of the set of performance values c.sub.n by a signal converter, comparing the performance value c.sub.j with a reference value c.sub.ref by a controller, resulting in a deviation value c, and controlling an actuator by using the deviation c for regulating the local global process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.

A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period. Accordingly, a characteristic of the electrical quantity at each of the respective test output conductors over the duration of the longest period of the unique periods is indicative of any disturbance between the discrete output signals associated with the test output conductor and all of the other discrete output signals.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

The present disclosure relates to a display panel, and a display device including the same. The display panel includes a display area, including M scan lines and N data lines that are intersected, and a plurality of sub-pixels located in a sub-pixel area defined by respective scan lines and data lines, a first test area, comprising N first switching elements having a first end connected to a test signal end, and a control end connected to a first control signal, and N auxiliary switching elements having a first end connected to the nth data line, a second end connected to a second end of the nth first switching element, and the control end connected to a second control signal line; wherein, M and N are positive integers, and nN.

An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

The invention relates to a real-time oscilloscope with a built-in time domain reflectometry (TDR) and/or time-domain transmission (TDT) function for measurements of a device under test (DUT). The real-time oscilloscope comprises at least one built-in generator and at least one real-time measurement channel. The built-in generator is in communication with the real-time measurement channel and the device under test (DUT) and is configured to generate incident signals. The real-time measurement channel is configured to capture incident signals transmitted to and reflected by and/or transmitted by the device under test (DUT).

A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

Systems and methods for monitoring operating conditions of a programmable device are disclosed. The system may include a root monitor configured to generate a reference voltage, a plurality of sensors distributed across the device, and a plurality of satellite monitors distributed across the device. Each of the satellite monitors may be coupled to a corresponding sensor via a local interconnect, and may be configured to convert analog signals generated by the sensor into digital data indicative of one or more operating conditions of an associated circuit. In some implementations, each satellite monitor may include a circuit to store a local reference voltage, an analog-to-digital converter (ADC) to convert the analog signals into digital codes, a calibration circuit to generate a correction factor indicative of errors in the digital codes, and a correction circuit to correct the digital codes based on the correction factor.