A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Systems, methods, and circuitries are disclosed to test an inter-domain device that is positioned in a signal path between a first output wrapper device in a first module and a first input wrapper device in a second module. In one example, a testing system includes an output scan chain that includes the first output wrapper device and an input scan chain that includes the first input wrapper device. A controller is configured to: provide an output scan enable signal to the output scan chain to cause test data to be stored in the first output wrapper device; capture, with the first input wrapper device, inter-domain device data output; provide an input scan enable signal to the input scan chain to cause the inter-domain device data to be output by an output scan chain serial output; and determine whether the inter-domain device data indicates that the inter-domain device is defective.

A method and interface circuit for testing an electronic device with a single logic pin is disclosed. The comprises forming a data stream having three level bands; inputting the data stream through a single logic pin; and decoding the data stream to identify a scan_in signal, a scan_shift_enable signal and a scan_out signal and returning contemporaneously a scan_out signal as an output through the same logic pin. The interface circuit includes a decoder connected to the single logic pin.

A safety circuit for the multi-channel processing of an input signal. The safety circuit includes an analog-to-digital conversion device having a first analog input and a second analog input and at least one digital output for processing the input signal. Furthermore, the safety circuit has a test device which is set up to apply a test signal at the first and/or second input of the A/D conversion device in such a way that the test signal superposes the input signal such that the test signal dominates the input signal.

A method for real-time testing of a control unit with a simulator is provided. The simulator calculates a load current and a load voltage as electrical load state variables via converter control data and via an electrical load model that does not take into account current discontinuities caused by the converter, and transmits at least a portion of the load state variables to the control unit. A control observer is additionally implemented on the simulator that calculates at least the load current as a load state variable taking into account the converter control data and an observer load model. The observer detects a zero-crossing of the load current and a current discontinuity caused thereby from the calculated load current, and upon detection of a current discontinuity the observer calculates an electrical compensating quantity.

A controller system includes a microprocessor having a sequencer configured to output at least one spare multiplexor control signal, a memory, and a plurality of sensor inputs. At least one stimulation circuit is connected to a sensor signal line. The at least one stimulation circuit being connected to the at least one spare multiplexor control signal. The stimulation circuit is configured such that a state of the at least one spare multiplexor control signal controls a state of the stimulation circuit.

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one wrapped core (40,100) (a core 100 surrounded by a wrapper boundary register (40) as wrapper chain). Test flexibility and speed of testing the core (100) are also improved. Suggested serial test interface comprises a state machine (210) and an instruction register (213) for wrapper-instructions, supplied through a single physical data input terminal (1a). The state machine (210) reads wrapper-instructions held by the instruction register (213) and generates on-chip wrapper control signals (30) of the given standard for the wrapper boundary register (40) of the core (100). At least one wrapper-instruction read from the Instruction Register (213) provides at least one wrapper control signal (30). The single input terminal (1a) also supplies an input test signal SDI for coupling to the wrapper boundary register (40) as on chip logical input test signal WSI. A single output terminal (1b) returns an output test signal SDO from an output WSO of the wrapper boundary register (40). Invention may apply to IEEE 1500 control signals.

An electronic chip includes an analog input connection pad and an analog output connection pad. A switch is coupled between the analog input connection pad and the analog output connection pad. In one embodiment, the chip operates in a self-test mode and in an active mode. The switch is closed only in the self-test mode.