An inspection circuit for inspecting a connection state between a semiconductor storage element including a storage section, and a semiconductor element connected to the semiconductor storage element, the inspection circuit includes: an input terminal that is input with a test signal to be sent to a first controller; an input/output terminal that is input and output with data to be written to or read from the storage section; a first inspection section that is input with an inspection signal; a second inspection section, disposed between the input terminal and the first controller, that converts the test signal to a control signal at a predetermined logic level under control of the first inspection section; and a third inspection section, disposed between the input/output terminal and a second controller, that sends the test signal to the second controller under control of the first inspection section.

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. Further operation of the target transaction master 8 is emulated using the model transaction master 32 using the opening state data. Diagnostic operations are performed upon the model transaction master 32. When the model transaction master 32 emulates initiation of a memory transaction with a memory address mapped to one of the target transaction slaves 12, 14, 16, this initiates the memory transaction to be performed with the target apparatus 2. Pages of stored values from the memory address space of the target apparatus 2 may be cached within the emulation.

A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.

A superconducting circuit is disclosed for fast digital readout of on-chip diagnostics in an array of devices in an integrated circuit. The digital readout comprises a digital RSFQ multiplexer to select the readout channel. This permits a large number of devices to be tested with a minimum of input and output lines. The devices may comprise digital devices (such as elementary RSFQ cells), or analog devices (such as inductors, resistors, or Josephson junctions) with a SQUID quantizer to generate a digital signal. The diagnostic array and the digital multiplexer are preferably configured to operate as part of the same integrated circuit at cryogenic temperatures.

Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.

System, method for circuit validation, and system and method for facilitating circuit validation are provided. The circuit validation system comprises a prototype system and a computing device. The prototype system comprises a programming logic device circuit configured to implement a modified circuit design. The modified circuit design includes a circuit module as a design under test (DUT), an input generation circuit coupled to the circuit module for outputting input signals to the circuit module in response to a test signal, and an output acquisition circuit coupled to the circuit module for storing output data from the circuit module. The computing device is capable of being coupled to the prototype system and configured to generate the test signal to perform a test of the DUT on the prototype system.

Configurable probe blocks for system monitoring are disclosed. Example apparatus disclosed herein include a processor to perform operations including enabling, based on a value of a control word, a first probe input of a probe block, the first probe input mapped to a source of monitored network traffic in a software defined network. Disclosed example apparatus also include configuring, based on the value of the control word, a first trigger condition of the probe block to evaluate the monitored network traffic to determine whether the monitored network traffic has a first characteristic. Disclosed example apparatus further include configuring, based on the value of the control word, a first probe output of the probe block to output a result of the monitored network traffic being evaluated according to the first trigger condition, the first probe output to output the result to a network application of the software defined network.

A controller system includes a microprocessor having a sequencer configured to output at least one spare multiplexor control signal, a memory, and a plurality of sensor inputs. At least one stimulation circuit is connected to a sensor signal line. The at least one stimulation circuit being connected to the at least one spare multiplexor control signal. The stimulation circuit is configured such that a state of the at least one spare multiplexor control signal controls a state of the stimulation circuit.