Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.

Apparatus for testing an integrated circuit is described, including a set of signal conductors for communicating signals to respective external conductors of the integrated circuit. The apparatus also includes a tester comprising circuitry for outputting a signal. An interposer is electrically coupled between the set of signal conductors and the tester. The interposer comprises circuitry for selecting a set of signals between the set of signal conductors and the tester and outputting the set of signals. A signal processing apparatus is coupled to receive the set of signals, and the signal processing apparatus is operable to evaluate a parameter associated with each signal in the set of signals.

A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

A method for identifying outlier devices during testing, includes: establishing binning limits for a device being tested based on one or more rules generated from external test results data of tests involving similar devices; receiving test results data in real time for the device being tested while the device is on a device tester; applying the one or more rules to the test results data for the device in real time; determining in real time, based on results of applying the one or more rules to the test results data, whether the device is an outlier with respect to the binning limits; and in response to determining that the device is an outlier, binning the outlier device separately from tested devices having test results data falling within the binning limits.

A test and measurement system for parallel waveform analysis acquires waveforms resulting from performing tests on a device under test (DUT) and performs, at least partially in parallel, respective analyses of the waveforms resulting from performing tests on the DUT. The system also acquires a first waveform resulting from performing a first test with an oscilloscope on a DUT and performs analysis of the first waveform at least partially in parallel with acquiring a second waveform. Additionally, the system tracks a plurality of testing assets using inventory information of a plurality of testing equipment on the network and enables remote users to access equipment logs and results of the respective analyses of the waveforms stored on a cloud computing system for performance of analytics.

Provided is an apparatus including a generating section that generates an altered test candidate obtained by adding an alteration shortening an execution time of a test to a target test for testing a device under test; a test processing section that causes a test apparatus to perform the altered test candidate on the device under test; and a comparing section that compares an altered test result of the device under test resulting from the altered test candidate to a target test result of the device under test resulting from the target test; and a judging section that judges whether the target test can be replaced by the altered test candidate, based on the comparison result of the comparing section.

A computer-implemented method for testing a system for at least one requirement. The method includes: the requirement is received in machine-readable form, at least one first input variable is ascertained for the test of the system for the received requirement, a design of the system is simulated as a function of the ascertained first input variable, an output variable of the simulated system is ascertained and it is ascertained as a function of the output variable whether the system meets the requirement, it is checked whether the simulation meets a quality requirement, if the simulation meets the quality requirement and the system meets the requirement, it is checked whether a sufficient test coverage is reached for the requirement, if the sufficient test coverage for the requirement is reached, the test for the requirement is completed.

A system for performing an automated test is disclosed. The method comprises receiving a plurality of work orders and a plurality of constraints for scheduling a plurality of tests on a plurality of DUTs using automated test equipment (ATE) available on a production floor, wherein the ATE comprises a plurality of test cells, and wherein each test cell comprises a plurality of testers and an automated handler. The method further comprises developing a test plan to execute the plurality of tests, wherein the test plan is customized in accordance with the information in the plurality of work orders and the plurality of constraints. Finally, the method comprises scheduling the plurality of tests to the plurality of test cells to maximize throughput of the plurality of DUTs.

A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.