A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

A state output circuit that outputs a state signal indicating a state of a power supply apparatus, including: a state output terminal that outputs the state signal; a reference potential line to which a reference potential is applied; a first pull-up terminal to which a first pull-up potential is applied, wherein the first pull-up potential is a potential higher than the reference potential; a connection switch unit that is provided between the state output terminal and the reference potential line, and switches whether to connect the state output terminal to the reference potential line or not, in accordance with the state of the power supply apparatus; a first protection resistor provided between the connection switch unit and the state output terminal; and a pull-up unit that pulls up a first connection line between the first protection resistor and the connection switch unit up to the first pull-up potential.

According to one embodiment, a design support device executes a first processing. The first processing includes setting a control value group for a semiconductor element. The semiconductor element includes gates including first and second gates. The control value group includes a first time difference between first and second timings. A voltage is applied to the first gate at the first timing. A voltage is applied to the second gate at the second timing. The first processing includes calculating a characteristic value from an output result when an electrical signal corresponding to the control value group is input to the semiconductor element. The first processing includes calculating a first function from history data including not less than one data set. The data set includes the control value group and a score based on the characteristic value. The design support device sets a new control value group.

The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.

An apparatus for testing components for use in a power system includes at least one power amplifier circuit configured to be coupled to the component and a control circuit configured to operate the power amplifier circuit responsive to at least one state of a component emulator for the component included in a system emulator for the power system. The component emulator may include at least one power electronics converter circuit and the control circuit may be configured to control at least one of a voltage and a current of the at least one power amplifier circuit responsive to at least one of a voltage and a current of the at least one power electronics converter circuit. The control circuit may be further configured to control the component emulator responsive to at least one state of the at least one power amplifier circuit.

An integrated circuit is provided that comprise a receive unit to be tested for receiving an input signal and storing the input signal at a predetermined point of time. Additionally, it comprises a processor for applying an error correction to the received input signal, for comparing the error corrected signal with an expectation value and for outputting an error message when the filtered input signal does not correspond to the expectation value. A power source supplies the receive unit to be tested with an adjustable voltage and/or and adjustable current. An adjustment unit varies the predetermined point in time and the adjustable voltage respectively the adjustable current.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

A voltage application device of a tester includes a voltage setting controller that sets a number of transient steps, step time, and step voltage as transient voltage setting parameters; and a device power supply (DPS) configured to supply power to the plurality of devices under test formed on a substrate. The voltage application device outputs an output voltage having a step-like transient voltage waveform based on the transient voltage setting parameters set by the voltage setting controller. The voltage application device is a high-order lag system of a second-order or higher in which an overshoot occurs in a response with respect to a set voltage. An end point of a step time of each of the transient steps set in the voltage setting controller is set to be a time between an end point of a rising time and an overshoot time.

Provided is an apparatus including a generating section that generates an altered test candidate obtained by adding an alteration shortening an execution time of a test to a target test for testing a device under test; a test processing section that causes a test apparatus to perform the altered test candidate on the device under test; and a comparing section that compares an altered test result of the device under test resulting from the altered test candidate to a target test result of the device under test resulting from the target test; and a judging section that judges whether the target test can be replaced by the altered test candidate, based on the comparison result of the comparing section.

A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.