A package structure is provided. The package structure includes at least one optoelectronic device, a lead frame, and an encapsulant. The optoelectronic device is disposed on the lead frame. The lead frame includes at least one lead unit that includes a first lead and a second lead. The first lead has a first bonding part and a first pin. The first bonding part has a first inclined sidewall at an upper end of one side away from the second lead. The second lead has a second pin and a carrying part, of which an upper end has a die-attaching region for carrying the optoelectronic device. The encapsulant covers at least the optoelectronic device, the first bonding part, and the carrying part.

A photonic integrated circuit (PIC) package comprising a first die, the first die comprising a first optical waveguide and a first trench extending from a first edge of the first die to the first optical waveguide. The first trench is aligned with the first optical waveguide. A second die comprises a second optical waveguide and a second trench extending from a second edge of the second die to the second optical waveguide. The second trench is aligned with the second optical waveguide. An optical wire comprising an uncladded glass fiber comprises a first terminal portion extending within the first trench and a second terminal portion extending within the second trench. The first terminal portion is aligned with the first optical waveguide and the second terminal portion is aligned with the second optical waveguide.

Various embodiments provide for computational systems including multiple circuit packages, each circuit package comprising an electronic integrated circuit having multiple processing elements and intra-chip bidirectional photonic channels connecting the processing elements into an electro-photonic network, with inter-chip bidirectional photonic channels connecting the processing elements across the electro-photonic networks of the multiple circuit packages into a larger electro-photonic network.

Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a vertically oriented semiconductor waveguide with a first end on a semiconductor layer. The vertically oriented semiconductor waveguide includes a first sidewall and a second sidewall opposite the first sidewall. A reflective material is along the second sidewall of the vertically oriented semiconductor waveguide. A first plurality of grating protrusions extends from the first sidewall of the vertically oriented semiconductor waveguide.

Optical beam forming at the inputs/outputs of a photonic chip and to the spectral broadening of the light coupled to the chip. The photonic chip comprises an optical waveguide layer supported on a substrate. The chip includes an optical waveguide structure made of silicon and a coupling surface grating. The photonic chip has a front face on the side facing the coupling surface grating and a rear face on the side facing the substrate. A reflecting collimation structure is integrated in the rear face to modify the mode size of an incident light beam. The coupling surface grating is designed to receive light from the optical waveguide structure and to form a light beam directed to the reflecting collimation structure. The invention further relates to the method for producing such a chip.

A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

An integrated optical component, including a transparent pad arranged on the upper face of the basic optical component, the transparent pad including a plane mirror at its upper face, and the basic optical component including a convergent mirror at its upper face, the plane and convergent mirrors being arranged such that the light beam is propagated between the internal light gate and the external light gate by passing through the transparent pad by reflection on the plane mirror and by reflection on the convergent mirror.

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.