A photonic integrated circuit (PIC) package comprising a first die, the first die comprising a first optical waveguide and a first trench extending from a first edge of the first die to the first optical waveguide. The first trench is aligned with the first optical waveguide. A second die comprises a second optical waveguide and a second trench extending from a second edge of the second die to the second optical waveguide. The second trench is aligned with the second optical waveguide. An optical wire comprising an uncladded glass fiber comprises a first terminal portion extending within the first trench and a second terminal portion extending within the second trench. The first terminal portion is aligned with the first optical waveguide and the second terminal portion is aligned with the second optical waveguide.

A photonic integrated circuit (PIC) package comprising a first die, the first die comprising a first optical waveguide and a first trench extending from a first edge of the first die to the first optical waveguide. The first trench is aligned with the first optical waveguide. A second die comprises a second optical waveguide and a second trench extending from a second edge of the second die to the second optical waveguide. The second trench is aligned with the second optical waveguide. An optical wire comprising an uncladded glass fiber comprises a first terminal portion extending within the first trench and a second terminal portion extending within the second trench. The first terminal portion is aligned with the first optical waveguide and the second terminal portion is aligned with the second optical waveguide.

A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

A package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.

A package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.

According to an aspect of the present disclosures, a method of making a flexible printed circuit board, which includes a base film having an insulating property, a conductive pattern disposed on either one or both surfaces of the base film, and a cover layer covering a conductive-pattern side of a laminated structure inclusive of the base film and the conductive pattern, includes a superimposing step of superimposing a cover film on the conductive-pattern side of the laminated structure, the cover film having a first resin layer and a second resin layer that is laminated to an inner side of the first resin layer and that softens at a lower temperature than does the first resin layer, and a pressure bonding step of vacuum bagging the laminated structure and the cover film at a temperature higher than a softening temperature of the second resin layer.