An opto-electric hybrid board connector includes an opto-electric hybrid board, a connector, and an adhesive member. The board has a bottom surface, a first side surface, and a second side surface. The connector has an inner bottom surface, a first inner side surface, and a second inner side surface. The adhesive member includes a first adhesive member having contact with the inner bottom surface, first inner side surface, and first side surface facing a first gap, and a second adhesive member filled in the first gap and having contact with the inner bottom surface, second inner side surface, and second side surface facing a second gap. A ratio (L1/L0) of a width L1 of the first gap to a width L0 of the inner bottom surface, and a ratio (L2/L0) of a width L2 of the second gap to the width L0 of the inner bottom surface are 0.01 or more.

Various embodiments provide for computational systems including multiple circuit packages, each circuit package comprising an electronic integrated circuit having multiple processing elements and intra-chip bidirectional photonic channels connecting the processing elements into an electro-photonic network, with inter-chip bidirectional photonic channels connecting the processing elements across the electro-photonic networks of the multiple circuit packages into a larger electro-photonic network.

Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

Optical beam forming at the inputs/outputs of a photonic chip and to the spectral broadening of the light coupled to the chip. The photonic chip comprises an optical waveguide layer supported on a substrate. The chip includes an optical waveguide structure made of silicon and a coupling surface grating. The photonic chip has a front face on the side facing the coupling surface grating and a rear face on the side facing the substrate. A reflecting collimation structure is integrated in the rear face to modify the mode size of an incident light beam. The coupling surface grating is designed to receive light from the optical waveguide structure and to form a light beam directed to the reflecting collimation structure. The invention further relates to the method for producing such a chip.

An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.