G02F2201/508

ELECTROCHROMIC DEVICE INCLUDING A TRANSPARENT CONDUCTIVE OXIDE LAYER AND A BUS BAR AND A PROCESS OF FORMING THE SAME
20170299934 · 2017-10-19 ·

An electrochromic device can include a substrate, a transparent conductive oxide layer over the substrate, and a bus bar over the substrate. The bus bar can include silver and has a resistivity of at most 6.7×10.sup.−6 Ω*cm, an average adhesion strength to SiO.sub.2 of at least 3N based on 20 measurements, as determined by Method A of ASTM B905-00 (Reapproved 2010), or a classification of at least 4, as determined by Method B of ASTM B905-00 (Reapproved 2010). In another aspect a process of forming an electrochromic device can include forming a transparent conductive oxide layer over a substrate; forming a bus bar precursor over the substrate, wherein the precursor includes silver; and firing the precursor to form a bus bar. Firing can be performed such that the first bus bar is at a temperature of at least 390° C.

Fabrication of electrochromic devices

Electrochromic devices and methods may employ the addition of a defect-mitigating insulating layer which prevents electronically conducting layers and/or electrochromically active layers from contacting layers of the opposite polarity and creating a short circuit in regions where defects form. In some embodiments, an encapsulating layer is provided to encapsulate particles and prevent them from ejecting from the device stack and risking a short circuit when subsequent layers are deposited. The insulating layer may have an electronic resistivity of between about 1 and 10.sup.8 Ohm-cm. In some embodiments, the insulating layer contains one or more of the following metal oxides: aluminum oxide, zinc oxide, tin oxide, silicon aluminum oxide, cerium oxide, tungsten oxide, nickel tungsten oxide, and oxidized indium tin oxide. Carbides, nitrides, oxynitrides, and oxycarbides may also be used.

Liquid crystal display panel

A liquid crystal display panel includes: a plurality of pixels arranged in a matrix; a plurality of pixel electrodes and a plurality of transistors provided in each of the plurality of pixels; and a scanning line connected to the plurality of transistors in each of the plurality of pixels arranged in a first direction. In each of the plurality of pixels, the plurality of pixel electrodes and the plurality of transistors are arranged in the first direction.

Display device including a patterned conductive layer
11233073 · 2022-01-25 · ·

A display device includes: a gate line including a gate line portion; a data line; a transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; and a connecting member disposed between the data line and the source electrode, connected to the data line and the source electrode to cross a gate electrode edge of the gate electrode. A connecting portion where a data line edge and a connecting member edge are connected to each other does not overlap the gate line and the gate electrode in a plan view. The data line includes a first data line portion crossing the gate line and a second data line portion connected to the first data line portion and does not overlap the gate line in the plan view.

Display device including a patterned conductive layer
11784192 · 2023-10-10 · ·

A display device includes: a gate line including a gate line portion; a data line; a transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; and a connecting member disposed between the data line and the source electrode, connected to the data line and the source electrode to cross a gate electrode edge of the gate electrode. A connecting portion where a data line edge and a connecting member edge are connected to each other does not overlap the gate line and the gate electrode in a plan view. The data line includes a first data line portion crossing the gate line and a second data line portion connected to the first data line portion and does not overlap the gate line in the plan view.

FABRICATION OF ELECTROCHROMIC DEVICES

Electrochromic devices and methods may employ the addition of a defect-mitigating insulating layer which prevents electronically conducting layers and/or electrochromically active layers from contacting layers of the opposite polarity and creating a short circuit in regions where defects form. In some embodiments, an encapsulating layer is provided to encapsulate particles and prevent them from ejecting from the device stack and risking a short circuit when subsequent layers are deposited. The insulating layer may have an electronic resistivity of between about 1 and 10.sup.8 Ohm-cm. In some embodiments, the insulating layer contains one or more of the following metal oxides: aluminum oxide, zinc oxide, tin oxide, silicon aluminum oxide, cerium oxide, tungsten oxide, nickel tungsten oxide, and oxidized indium tin oxide. Carbides, nitrides, oxynitrides, and oxycarbides may also be used.

FABRICATION OF ELECTROCHROMIC DEVICES

Electrochromic devices and methods may employ the addition of a defect-mitigating insulating layer which prevents electronically conducting layers and/or electrochromically active layers from contacting layers of the opposite polarity and creating a short circuit in regions where defects form. In some embodiments, an encapsulating layer is provided to encapsulate particles and prevent them from ejecting from the device stack and risking a short circuit when subsequent layers are deposited. The insulating layer may have an electronic resistivity of between about 1 and 10.sup.8 Ohm-cm. In some embodiments, the insulating layer contains one or more of the following metal oxides: aluminum oxide, zinc oxide, tin oxide, silicon aluminum oxide, cerium oxide, tungsten oxide, nickel tungsten oxide, and oxidized indium tin oxide. Carbides, nitrides, oxynitrides, and oxycarbides may also be used.

MITIGATING DEFECTS IN AN ELECTROCHROMIC DEVICE UNDER A BUS BAR

Methods are provided for fabricating electrochromic devices that mitigate formation of short circuits under a top bus bar without predetermining where top bus bars will be applied on the device. Devices fabricated using such methods may be deactivated under the top bus bar, or may include active material under the top bus bar. Methods of fabricating devices with active material under a top bus bar include depositing a modified top bus bar, fabricating self-healing layers in the electrochromic device, and modifying a top transparent conductive layer of the device prior to applying bus bars.

Silicon Photonic Device With Backup Light Paths
20230375862 · 2023-11-23 ·

A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.

DISPLAY DEVICE INCLUDING A PATTERNED CONDUCTIVE LAYER
20220109007 · 2022-04-07 ·

A display device includes: a gate line including a gate line portion; a data line; a transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; and a connecting member disposed between the data line and the source electrode, connected to the data line and the source electrode to cross a gate electrode edge of the gate electrode. A connecting portion where a data line edge and a connecting member edge are connected to each other does not overlap the gate line and the gate electrode in a plan view. The data line includes a first data line portion crossing the gate line and a second data line portion connected to the first data line portion and does not overlap the gate line in the plan view.