A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

Computer-implemented systems and methods for automatically eliminating connectivity mismatches in a mask layout block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints. Disclosed systems and methods analyze a physical connection of a selected polygon or net in a mask layout block and obtain connectivity information associated with the selected polygon or net from a netlist or external constraints file. The physical connection of the selected polygon or net is compared with the obtained connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net. If there is a determined connectivity mismatch, a violation marker representing the connectivity mismatch is generated and the connectivity mismatch is corrected by placing, moving, or editing the selected polygon or net to modify the physical connection.

In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.

Methods for patterning a substrate are described. A substrate is scanned using a spatial light modulator with a plurality of exposures timed according to a non-crystalline shot pattern. Lithography systems for performing the substrate patterning method and non-transitory computer-readable medium for executing the patterning method are also described.

Some implementations described herein provide an exposure tool and associated methods of operation in which a scanner control system generates a scanner route for an exposure recipe such that the distance traveled by a substrate stage of the exposure tool along the scanner route is reduced and/or optimized for non-exposure fields on a semiconductor substrate. In this way, the scanner control system increases the productivity of the exposure tool, reduces processing times of the exposure tool, and increases yield in a semiconductor fabrication facility in which the exposure tool is included.

A layout geometry of a lithographic mask is received. The layout geometry includes at least one shape having one or more rounded corners. The layout geometry is partitioned into a plurality of feature images, for example as selected from a library. The feature images include at least one mask corner rounding (MCR)-corrected feature image that accounts for the rounded corners of the shape. The feature images have corresponding mask 3D (M3D) filters, which represent the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the mask illuminated by the source illumination.

A method for determining process window limiting patterns based on aberration sensitivity associated with a patterning apparatus. The method includes obtaining (i) a first set of kernels and a second set of kernels associated with an aberration wavefront of the patterning apparatus and (ii) a design layout to be printed on a substrate via the patterning apparatus; and determining, via a process simulation using the design layout, the first set of kernels, and the second set of kernels, an aberration sensitivity map associated with the aberration wavefront, the aberration sensitivity map indicating how sensitive one or more portions of the design layout are to an individual aberrations and an interaction between different aberrations; determining, based on the aberration sensitivity map, the process window limiting pattern associated with the design layout having relatively high sensitivity compared to other portions of the design layout.

Methods of generating a characteristic pattern for a patterning process and training a machine learning model. A method of training a machine learning model configured to generate a characteristic pattern for a mask pattern includes obtaining (i) a reference characteristic pattern that meets a satisfactory threshold related to manufacturing of the mask pattern, and (ii) a continuous transmission mask (CTM) for use in generating the mask pattern; and training, based on the reference characteristic pattern and the CTM, the machine learning model such that a first metric between the characteristic pattern and the CTM, and a second metric between the characteristic pattern and the reference characteristic pattern is reduced.