An overlay compensation method can be applied to a wafer, and include: acquiring overlays of an exposed wafer; dividing the exposed wafer into a plurality of regions; calculating compensation values corresponding to the regions respectively according to the overlays corresponding to the regions; and compensating corresponding regions of a to-be-exposed wafer respectively by using the compensation values. The overlay compensation method, the exposure system, the server and the computer-readable storage medium can improve the accuracy of overlay compensation for a wafer and improve a product yield.

Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.

A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.

The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for Hessian-Free photolithography mask optimization. The method includes steps: S1, inputting a design layout of a mask to be optimized; S2, positioning error monitoring points on the design layout of the mask to be optimized; S3, obtaining an optimization variable x of the mask to be optimized; S4, forming an objective function cost on the optimization variable x; and S5, optimizing the objective junction cost by a Hessian-Free-based conjugate gradient method, to obtain an optimization result of the mask to be optimized. Optimizing the objective function cost based on a Hessian-Free conjugate gradient method to obtain an optimization result of the mask to be optimized, which can greatly reduce the computation resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency. Meanwhile, there is no need to use the quasi-Newton method to obtain the approximate replacement matrix of the H matrix, which can improve the accuracy of the optimization result.

According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

In one embodiment, a method includes receiving measured linescan information describing a pattern structure of a feature, applying the received measured linescan information to an inverse linescan model that relates measured linescan information to feature geometry information, and identifying, based at least in part on the applying the received measured linescan model to the inverse linescan model, feature geometry information that describes a feature that would produce a linescan corresponding to the received measured linescan information. The method also includes determining, at least in part using the inverse linescan model, feature edge positions of the identified feature, analyzing the feature edge positions to determine errors in the manufacture of the pattern structure, and controlling a lithography tool based on the analysis of the feature edge positions.

In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Embodiments of the systems, methods, and software provided herein patterns substrates using digital lithography patterning controlled by field programmable gate arrays (FPGA). Stage position data is provided to the FPGA from the lithography environment and the data is loaded into a memory from the FPGA. The graphics processing unit, reads the data from the memory and calculates instructions based on the data. At least a portion of a substrate disposed on the stage is processed using instructions provided by the FPGA.

The present disclosure provides a method and a system for generating photomask patterns. The system obtains a design layout image, and generates a hotspot image corresponding to the design layout image based on a hotspot detection model. The system generates two photomask patterns based on the hotspot image. The at least two photomask patterns are transferred onto a semiconductor substrate.

A method for determining a likelihood that an assist feature of a mask pattern will print on a substrate. The method includes obtaining (i) a plurality of images of a pattern printed on a substrate and (ii) variance data the plurality of images of the pattern; determining, based on the variance data, a model configured to generate variance data associated with the mask pattern; and determining, based on model-generated variance data for a given mask pattern and a resist image or etch image associated with the given mask pattern, the likelihood that an assist feature of the given mask pattern will be printed on the substrate. The likelihood can be applied to adjust one or more parameters related to a patterning process or a patterning apparatus to reduce the likelihood that the assist feature will print on the substrate.