The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for Hessian-Free photolithography mask optimization. The method includes steps: S1, inputting a design layout of a mask to be optimized; S2, positioning error monitoring points on the design layout of the mask to be optimized; S3, obtaining an optimization variable x of the mask to be optimized; S4, forming an objective function cost on the optimization variable x; and S5, optimizing the objective junction cost by a Hessian-Free-based conjugate gradient method, to obtain an optimization result of the mask to be optimized. Optimizing the objective function cost based on a Hessian-Free conjugate gradient method to obtain an optimization result of the mask to be optimized, which can greatly reduce the computation resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency. Meanwhile, there is no need to use the quasi-Newton method to obtain the approximate replacement matrix of the H matrix, which can improve the accuracy of the optimization result.

The present disclosure relates to a lithography scanner including: a light source configured to emit extreme ultra-violet (EUV) light; a pellicle including an EUV transmissive membrane that is configured to scatter the EUV light into an elliptical scattering pattern having a first major axis; a reticle configured to reflect the scattered EUV light through the pellicle; and an imaging system configured to project a portion of the reflected light that enters an acceptance cone of the imaging system onto a target wafer, wherein a cross section of the acceptance cone has a second major axis, and wherein the pellicle is arranged such that the first major axis is oriented at an angle relative to the second major axis.

A method for determining an overlay metric is disclosed including obtaining angle resolved distribution spectrum data relating to a measurement of a target structure including a symmetrical component. An overlay dependent contour of a feature of the target structure is determined from the angle resolved distribution spectrum data, from which an overlay metric is determined. The method includes exposing an exposed feature onto a masked layer including a mask which defines masked and unmasked areas of the layer, such that a first portion of the exposed feature is exposed on a masked area of the layer and a second portion of the exposed feature is exposed on a non-masked area of the layer, the size of the first portion with respect to the second portion being overlay dependent; and performing an etch step to define an etched feature, the etched feature corresponding to the second portion of the exposed feature.

Described are methods for enabling the creation of multiple similar designs by utilizing sets of multiple, disjoint fabrication masks. A first set of device features may be formed from a material layer in a first portion of a die area of a semiconductor substrate based on a first photolithographic exposure. A second set of device features may be formed from the material layer in a second portion of the die area of the semiconductor substrate based on a second photolithographic exposure after the first photolithographic exposure. The first portion of the die area and the second portion of the die area may be non-overlapping.

A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.

A technique which determines an optimum die layout on a semiconductor wafer is disclosed. The technique determines the optimum die layout with a significantly reduced number of calculations compared to conventional brute force techniques. This enables the generation of the optimum die layout in a much shorter period of time, reducing design turn-around time. The optimum layout is used to process a wafer which produces the optimum number of dies.

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

A direct write exposure apparatus configured to process a plurality of substrates, the apparatus including: a substrate holder configured to hold a substrate having a usable patterning area; a patterning system configured to project different patterns onto the substrate; a processing system configured to: determine a first combination of one or more patterns that are to be applied on a first substrate of the plurality of substrates; and determine a second, different combination of one or more patterns that are to be applied on a second, subsequent, substrate of the plurality of substrates.

According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

A rasterization method of patterns with periodic components for SLMs is presented, comprising obtaining (S10) of an original pattern, having a periodicity. A first pattern main period is determined (S21). Image area and a first pitch of imaged elements are obtained (S31). The original pattern is scaled (S41) by a first raster scaling factor. The scaled pattern is cropped (S51) to comprise a first integer number of repetitions of the pattern items presenting a periodicity in the first direction that is covered by the image area, giving a rasterized pattern adapted to the intended pattern generator. The rasterized pattern is associated with data representing the first scaling factor. A writing method comprises obtaining of the rasterized pattern. Elements of the SLM in the pattern generator falling outside the rasterized pattern are set to be disabled. The rasterized pattern is written with an optical scaling to a target surface.