Patent classifications
G03F7/70475
EXPOSURE METHOD AND METHOD OF MANUFACTURING DISPLAY APPARATUS USING THE SAME
An exposure method for stepwise moving a rectangular mask and a relative position of a substrate includes first shot exposure in which the mask is located on a first region of the substrate, coordinates of two points on one side of the mask are detected, the mask is aligned using the coordinates, and then a first shot is exposed, second shot exposure in which the mask is located on a second region of the substrate, coordinates of two points on one side of the mask are detected, the mask is aligned using the coordinates, and then a second shot is exposed, and third shot exposure in which the mask is located on a third region of the substrate, coordinates of two points on one side of the mask are detected, the mask is aligned using the coordinates, and then a third shot is exposed.
MASK, EXPOSURE METHOD AND TOUCH DISPLAY PANEL
A mask is provided. The mask includes a plurality of light blocking strips configured to block light and bounding spaces through which light is allowed to pass. The plurality of light blocking strips are arranged in a mesh shape, and include first light blocking strips located in at least one side edge of the mask, and second light blocking strips, and each of the first light blocking strips has a greater width than each of the second light blocking strips. An exposure method using the mask, and a touch display panel manufactured by the exposure method are also provided.
MULTIPLE RETICLE FIELD SEMICONDUCTOR DEVICES
Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.
DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
A display panel including: a display portion including a plurality of signal lines and a plurality of pixels connected to the signal lines; a peripheral portion provided around the display portion; an integrated circuit (IC) mounting unit provided on the peripheral portion, and including a plurality of driver ICs connected to a data driver; and a test pad portion provided on the peripheral portion and testing the signal lines. The test pad portion includes a gate driver test pad portion including a gate driver test pad unit and a data line test pad unit including a data line test pad unit, the data line test pad unit includes an outermost data line test pad unit provided on respective sides of the data line test pad portion and a plurality of intermediate data line test pad units provided between the outermost data line test pad units.
Semiconductor Manufacturing Apparatus and Method Thereof
A method, comprising forming a material layer over a substrate; illuminating at least one region of the material layer with a light; recording strength of the light reflected from the at least one region; and determining a thickness of the material layer in the at least one region according to the strength of the light.
METHODS AND SYSTEMS FOR WAFER IMAGE GENERATION
A method is disclosed of generating a die tensor of a wafer from a Computer-Aided Design (CAD) file. According to the method, a segmentation engine segments a wireframe image obtained from the CAD file into a plurality of entities. An image transformation engine performs a transform on each of the plurality of entities based on at least one of the wireframe image, metrology, a design specification, process information, and optical information. The transform is performed iteratively based on the optical information. A stitch engine generates a die tensor, having a predefined number of slices, by combining each of the transformed plurality of entities.
METHODS AND SYSTEMS FOR WAFER IMAGE GENERATION
A method is disclosed of generating a die tensor of a wafer from a Computer-Aided Design (CAD) file. According to the method, a segmentation engine segments a wireframe image obtained from the CAD file into a plurality of entities. An image transformation engine performs a transform on each of the plurality of entities based on at least one of the wireframe image, metrology, a design specification, process information, and optical information. The transform is performed iteratively based on the optical information. A stitch engine generates a die tensor, having a predefined number of slices, by combining each of the transformed plurality of entities.
DYNAMIC GENERATION OF LAYOUT ADAPTIVE PACKAGING
Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.
Dynamic generation of layout adaptive packaging
Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.
System and method for aligned stitching
A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.