The present application discloses an image stitching method for a stitching product, which includes: step 1: providing a chip design layout of the stitching product; step 2: designing a mask layout according to the chip design layout, including: step 21: setting unit mask images; step 22: merging logic images or cutting path images of adjacent areas between unit regions together to set corresponding peripheral mask images; step 23: merging the same peripheral mask images into one; step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; step 3: performing repeated exposure to form the stitching product. The present application can reduce the number of mask images, the number of times of exposure and the time of exposure.

A system, methods, and a non-transitory computer-readable medium for digital lithography to reduce mura in substrate sections. The boundary lines of the digital lithography need to be invisible. In one example, a system includes a processing unit configured to print a virtual mask file provided by a controller. The controller is configured to receive data and convert the data into a virtual mask file having an exposure pattern for a lithographic process. The exposure pattern includes a plurality of first sections, and second sections. Each first section forms a boundary with each second section along a first column of image projection systems of the processing unit. The controller patterns the substrate. The exposure pattern includes a first section pattern of each first section that crosses the eye to eye boundary with the second section making the boundary invisible.

Compute complexes, base dies, and methods related to leveraging reticle stitching for improved device interconnects are discussed. A base die includes first and second regions having device layers, lower level metallization layers, and through vias fabricated using the same reticles. In the first region, a first subset of the through vias are contacted by higher metallization layers and, in the second region, a second distinct subset of the through vias are contacted by higher metallization layers such that the first and second metallization layers provide unique routing through vias having shared layouts and relative locations in the first and second regions.

The invention provides a display device that allows formation of the boundary of exposure at an arbitrary position on its substrate. A display device includes: a display area; a terminal; and a wire formed between the display area and the terminal and connected to the terminal. The wire includes a first part, a second part, and a third part. The first part extends in a first direction. The second part and the third part extend in a direction different from the first direction. The first part is located between the second and third parts and includes a protruding portion protruding in a second direction perpendicular to the first direction.

Reticles, line feature patterns, and methods are described related to improving overlay margins in reticle stitching applications. A first reticle to expose a first field includes a first portion of a line feature. The first portion has a pattern inclusive of one or more pattern features. The first reticle or a second reticle to expose a second field adjacent the first filed includes a second portion of the line feature. The second portion has an inverse pattern relative to the first pattern such that, when the first and inverse patterns are overlaid, a continuous merged region is formed.

A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

An extreme ultraviolet lithography system (10) that creates a pattern (230) having a plurality of densely packed parallel lines (232) on a workpiece (22) includes a patterning element (16); an EUV illumination system (12) that directs an extreme ultraviolet beam (13A) at the patterning element (16); a projection optical assembly (18) that directs the extreme ultraviolet beam diffracted off of the patterning element (16) at the workpiece (22); and a pattern blind assembly (26) positioned in a beam path (55) of the extreme ultraviolet beam (13A). The pattern blind assembly (26) shapes the extreme ultraviolet beam (13A) so that an exposure field (28) on the workpiece (22) has a polygonal shape.

A lithography system for generating grating structures is provided having a multiple column imaging system located on a bridge capable of moving in a cross-scan direction, a mask having a grating pattern with a fixed spatial frequency located in an object plane of the imaging system, a multiple line alignment mark aligned to the grating pattern and having a fixed spatial frequency, a platen configured to hold and scan a substrate, a scanning system configured to move the platen over a distance greater than a desired length of the grating pattern on the substrate, a longitudinal encoder scale attached to the platen and oriented in a scan direction and at least two encoder scales attached to the platen and arrayed in the cross-scan direction wherein the scales contain periodically spaced alignment marks having a fixed spatial frequency.

Disclosed herein an exposure apparatus capable of implementing a microfabrication onto a work with a higher throughput and a lower cost. The exposure apparatus generates interfering light by crossing two or more branched light beams branched from output light from a coherent light source at a predetermined interfering angle, and exposes the substrate by repeating an irradiation onto the substrate with the interfering light and a conveyance of the substrate. At this moment, the exposure apparatus shapes in interfering light irradiation region on the substrate onto which the interfering light is irradiated into a predetermined shape. Then, the exposure apparatus disposes a plurality of the interfering light irradiation regions in successive shots to be located adjacent to each other on the substrate in a direction of conveying the substrate without the interfering light irradiation regions being overlapped when exposing the substrate while conveying the substrate in a stepwise manner.

A touch sensor comprises a group pattern having a sensing cell part including a plurality of sensing cell groups in which a plurality of sensing cells are electrically connected and a wiring part formed outside the sensing cell part. The wiring part includes a first sub-wiring part and a second sub-wiring part. The first sub-wiring part has a drawing wire electrically connected to a sensing cell at one end of the sensing cell group. The second sub-wiring part is disposed outside the first sub-wiring part and has a non-drawing wire not electrically connected to the sensing cell part. The non-drawing wires are provided as many as the number of unit patterns repeatedly formed to constitute a large-area touch sensor minus one.