Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.

A photomask alignment method for a manufacturing process of an integrated circuit in a semiconductor material wafer (20), the method envisaging: at a first level, defining, by means of a single photolithography process, at least one alignment structure (10; 10) on the wafer (20), the alignment structure (10; 10) having at least a first (4a) and a second (4b) reference mark; and, at an upper level, higher than the first one, aligning a first field mask (11a) relative to the at least one first reference mark (4a); and aligning a second field mask (11b), which is used, together with the first field mask (11a), for the photolithography formation of the integrated circuit inside a respective die (22) in the wafer (20), relative to the at least one second reference mark (4b), so that the first and second field masks (11a, 11b) are arranged on the wafer (20) adjacent to one another in a first coupling direction, without any mutual overlapping.

In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.

Systems, methods and computer program products generally include a vector by vector subtraction method per wafer. A first layer is exposed to form a pattern image on a wafer and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a baseline reference are measured. The first layer is then reworked and exposed to form the same pattern image and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a first layer are measured. The overlay data of the reworked first layer is subtracted from the overlay data of the first layer to provide an overlay difference at each of the multiple locations. The overlay difference is converted to a pre-correction factor of a magnitude opposite that of the overlay difference and is applied to exposure of a second layer provided on the first layer.

An exposure apparatus includes: a first light source that generates first exposure light, a diaphragm having plurality of openings positioned between the first light source and an exposure photomask, a plurality of first projection optical systems that individually project an optical image realized by the first exposure light transmitted through each of the plurality of openings on an exposure target, a second light source that generates second exposure light, and a correction stepper. The correction stepper irradiates a light amount correction region with the second exposure light so as to limit an irradiation range of the exposure target to be irradiated with the second exposure light transmitted through the exposure photomask, and the light amount correction region is a region extending in a first direction by a width of a multi-opening region in a second direction in a plan view.

A display device including: a substrate having display area and a non-display area; and an alignment mark disposed in the non-display area of the substrate. The alignment mark includes a quadrangular-shaped center portion and a plurality of measurement portions that surround the center portion, the plurality of measurement portions including four or more measurement portions, and each of the measurement portions including sides that are parallel with two sides of the quadrangular-shaped center portion.

In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

Systems, methods and computer program products generally include a vector by vector subtraction method per wafer. A first layer is exposed to form a pattern image on a wafer and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a baseline reference are measured. The first layer is then reworked and exposed to form the same pattern image and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a first layer are measured. The overlay data of the reworked first layer is subtracted from the overlay data of the first layer to provide an overlay difference at each of the multiple locations. The overlay difference is converted to a pre-correction factor of a magnitude opposite that of the overlay difference and is applied to exposure of a second layer provided on the first layer.