Patent classifications
G03F9/7076
Imprint apparatus, imprinting method, and manufacturing method of article
An imprint apparatus using a mold having a pattern region includes an irradiation unit that irradiates a substrate with irradiation light. The irradiation light has an intensity distribution over a region along a periphery of a shot area of the substrate and being capable of increasing viscosity of an imprint material or of solidifying the imprint material. The imprint apparatus also includes a control unit that sets an imprint condition for forming a pattern of the imprint material so as to reduce at least one of an extrusion of the imprint material from the shot area and an unfilling of the imprint material occurring in the shot area on the basis of results of detecting at least one of the extrusion and the unfilling of the imprint material obtained by detecting the pattern of the imprint material formed on the substrate.
ALIGNMENT MARK SEARCHING METHOD, DISPLAY SUBSTRATE AND DISPLAY APPARATUS
An alignment mark searching method is for searching an alignment mark on a base substrate, a first positioning line segment is formed in a dummy region of the base substrate, and a straight line where the first positioning line segment is positioned running through the alignment mark. The method includes: acquiring theoretical coordinates of the alignment mark; moving a detection system view field to a target position with the theoretical coordinates as a target; moving the detection system view field from the target position in a direction perpendicular to the first positioning line segment until the first positioning line segment appears in the detection system view field; and moving the detection system view field from the position of the first positioning line segment in a length direction of the first positioning line segment until the alignment mark appears in the detection system view field. The method achieves an effect that the alignment mark can be simply, conveniently and rapidly searched. A display substrate and a display apparatus are further disclosed.
Methods and patterning devices and apparatuses for measuring focus performance of a lithographic apparatus, device manufacturing method
Disclosed is a method of measuring focus performance of a lithographic apparatus. The method comprises using the lithographic apparatus to print at least one focus metrology pattern on a substrate, the printed focus metrology pattern comprising at least a first periodic array of features, and using inspection radiation to measure asymmetry between opposite portions of a diffraction spectrum for the first periodic array in the printed focus metrology pattern. A measurement of focus performance is derived based at least in part on the asymmetry measured. The first periodic array comprises a repeating arrangement of a space region having no features and a pattern region having at least one first feature comprising sub-features projecting from a main body and at least one second feature; and wherein the first feature and second feature are in sufficient proximity to be effectively detected as a single feature during measurement. A patterning device comprising said first periodic array is also disclosed.
APPARATUS AND METHOD FOR MEASURING A POSITION OF A MARK
An apparatus for measuring a position of a mark on a substrate, the apparatus comprising: an illumination system configured to condition at least one radiation beam to form a plurality of illumination spots spatially distributed in series such that during scanning of the substrate the plurality of illumination spots are incident on the mark sequentially, and a projection system configured to project radiation diffracted by the mark from the substrate, the diffracted radiation being produced by diffraction of the plurality of illumination spots by the mark; wherein the projection system is further configured to modulate the diffracted radiation and project the modulated radiation onto a detecting system configured to produce signals corresponding to each of the plurality of illumination spots, the signals being combined to determine the position of the mark.
OVERLAY ALIGNMENT MARK, METHOD FOR MEASURING OVERLAY ERROR, AND METHOD FOR OVERLAY ALIGNMENT
An overlay alignment mark, a method for measuring overlay error, and a method for overlay alignment are provided in the embodiments of the present disclosure. the overlay alignment mark is formed on a wafer to be detected and comprises a first pattern and a second pattern, the first pattern being located in a first layer of the wafer and comprising two first solid sub-patterns which are provided opposite to each other in a first direction and extend in a second direction perpendicular to the first direction, respectively, and the second pattern being located in a second layer above the first layer of the wafer and comprising two first hollowed sub-patterns which are provided opposite to each other in the first direction and two to second hollowed sub-patterns which are provided opposite to each other in the second direction; and two opposite side edges of each of the two first solid sub-patterns extending in the second direction are at least partially exposed from a respective one of the two first hollowed sub-patterns.
Overlay Alignment Mark and Method for Measuring Overlay Error
An overlay alignment mark located in a patterned wafer and a method for measuring overlay error are provided, the patterned wafer having a lower-layer pattern in a first layer thereof and an upper-layer pattern in a second layer thereof above the first layer, the overlay alignment mark comprising: a first pattern, which is a portion of the lower-layer pattern and comprises a pair of solid features formed in the first layer; and a second pattern, which is a portion of the upper-layer pattern and comprises two pairs of hollowed features formed in the second layer, with two imaginary lines connecting between geometric centers of respective pairs in the two pairs of hollowed features extending in two mutually orthogonal directions, respectively; an orthographic projection of the pair of solid features on the wafer at least partially overlaps with an orthographic projection of a respective pair of hollowed features on the wafer.
Molding apparatus for molding composition on substrate with mold, and article manufacturing method
A molding apparatus that molds a composition on a substrate with a mold includes a mold holding unit configured to hold the mold, a substrate holding unit configured to hold the substrate, a first elastic member configured to apply a first elastic force to the mold holding unit in a direction away from the substrate holding unit, and a control unit configured to cause the mold holding unit to move in the direction away from the substrate holding unit in a case where the control unit determines that an abnormality has occurred.
Method to form a 3D integrated circuit
A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.
Scan signal characterization diagnostics
A system for and method of processing a wafer in which a scan signal is analyzed locally to extract information about alignment, overlay, mark quality, wafer quality, and the like.
FRAME REVEALS WITH MASKLESS LITHOGRAPHY IN THE MANUFACTURE OF INTEGRATED CIRCUITS
Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.