Implementations disclosed herein provide a method of reducing the topography at the alignment and overlay marks area during the writer pole photolithography process in order to reduce the wafer scale variation and reduce the writer pole photolithography process rework rate. In one implementation, an intermediate stage of a wafer for writer pole formation is generated by removing a part of at least one metallic writer pole layer on top of an intermediate stage writer pole wafer to form a recovery trench, depositing an optically transparent material on top of the wafer, wherein the thickness of the optically transparent material is higher than a target recovery trench topography, forming a photoresist pattern on top of the optically transparent material over the recovery trench, etching the optically transparent material, and removing the photoresist pattern and at least part of the remaining optically transparent material.

A lithography apparatus includes a formation unit that forms an alignment mark on a substrate by irradiating the substrate that includes a photosensitizer with light, and a transfer unit that aligns the substrate on the basis of the position of the alignment mark and that transfers a pattern to the substrate by illuminating the photosensitizer with exposure light. The formation unit irradiates a material of a grounding of the photosensitizer with irradiation light at a wavelength that differs from that of the exposure light and forms the alignment mark on the material by processing the material with energy of the irradiation light.

Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.

A patterning device, for use in forming a marker on a substrate by optical projection, the patterning device including a marker pattern having a density profile that is periodic with a fundamental spatial frequency corresponding to a desired periodicity of the marker to be formed. The density profile is modulated (such as sinusoidally) so as to suppress one or more harmonics of the fundamental frequency, relative to a simple binary profile having the fundamental frequency.

The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.

Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.

Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.

A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

In an optical circuit divided into a plurality of partial circuits, an optical waveguide having a low optical loss at a connection portion is provided. A photomask in which a waveguide pattern of an optical circuit is divided into a plurality of regions and drawn, the photomask including a waveguide pattern for drawing a joint region in which a waveguide width changes as a waveguide goes toward an outer peripheral portion, to connect a plurality of the waveguides divided and drawn to each other, in which the waveguides are connected to each other by overlapping the joint regions of two of the photomasks and performing exposure.

A sensor device provided in the disclosure includes a sensor substrate, a first transparent layer, a collimator layer, and a lens. The first transparent layer is disposed on the sensor substrate, wherein the first transparent layer defines an alignment structure. The collimator layer is disposed on the first transparent layer. The lens is disposed on the collimator layer.