Methods, systems, and apparatus for operations for performing a biometric recognition attack test on a biometric recognition device. An example method includes obtaining a biometric feature object for performing the biometric recognition attack on the biometric recognition device; Perform the biometric recognition attack test on the biometric recognition device, comprising: controlling a mechanical arm to place the biometric feature object in a recognition area of the biometric recognition device; and controlling the mechanical arm to press the biometric feature object to the biometric recognition device to trigger the biometric feature object to input the biometric features in the feature attachment part into the biometric recognition device through the conductive part; obtaining an attack test result corresponding to the biometric feature object; and determining a test result of the biometric recognition attack test performed on the biometric recognition device.

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

A multi-logic device system, an electronic engine controller, and a method of operating the multi-logic device system. The multi-logic device system includes a primary logic device which is more resilient to single event effects, and one or more secondary logic devices, each secondary logic device being powered by a respective power supply unit and being more susceptible to single event effects. The primary logic device is configured to run, for each secondary logic device, a respective watchdog timer. Each watchdog timer is restarted upon receipt of a restart signal from the respective secondary logic device. The primary logic device is also configured, in response to a watchdog timer timing out, to identify and reset the secondary logic device corresponding to the timed out watchdog timer.

A multi-logic device system, an electronic engine controller, and a method of operating the multi-logic device system. The multi-logic device system includes a primary logic device which is more resilient to single event effects, and one or more secondary logic devices, each secondary logic device being powered by a respective power supply unit and being more susceptible to single event effects. The primary logic device is configured to run, for each secondary logic device, a respective watchdog timer. Each watchdog timer is restarted upon receipt of a restart signal from the respective secondary logic device. The primary logic device is also configured, in response to a watchdog timer timing out, to identify and reset the secondary logic device corresponding to the timed out watchdog timer.

A method for controlling a plurality of driving functions in an automated or autonomous vehicle, a control unit designed to carry out the method, a computer program, and a machine-readable memory medium on which the computer program is stored are provided. In the method, the plurality of driving functions is described in each case by finite state machines. At least one finite state machine is of the Moore type, and includes a structure with a finite set of states. The states are linked to one another via edges. An edge defines from the finite set of states a transition from a starting state to a target state, in that an associated edge condition is true or false. The finite state machine is accessible during runtime based on the structure, so that an access to the states and the edges is made possible to change the states and/or the edges.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

A system includes a plurality of control devices that respectively control the states of a plurality of apparatuses and are connected to each other via communication lines. When each of the control devices determines a state target value of its own apparatus using the current state indicator value of the own apparatus, and the distributed controller input which is a function of the state indicator value of an apparatus adjacent to the own apparatus and the state indicator value of the own apparatus, the control gain which adjusts contribution of the distributed controller input to the state target value is determined based on a communication delay time between the control devices.

A system includes a plurality of control devices that respectively control the states of a plurality of apparatuses and are connected to each other via communication lines. When each of the control devices determines a state target value of its own apparatus using the current state indicator value of the own apparatus, and the distributed controller input which is a function of the state indicator value of an apparatus adjacent to the own apparatus and the state indicator value of the own apparatus, the control gain which adjusts contribution of the distributed controller input to the state target value is determined based on a communication delay time between the control devices.