Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuity on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.

Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuity on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.

A management apparatus monitors and/or controls a facility device. The management apparatus includes a setting unit, a storage unit, a determination unit, and an extraction unit. The setting unit sets association information associating identification information in order to specify a register used by the facility device with a data point regarding monitoring and/or control of the facility device. The storage unit stores history information that is association information previously set by the setting unit. The determination unit determines the use state of the register in the facility device. The extraction unit extracts the history information identical or similar to the use state of the register determined by the determination unit from the history information.

Method for configuring an actuator (2) for the operation of a moving element (3) for closure, solar protection, privacy or screening, said actuator comprising a gear motor (4) and a gear motor electronic control unit (5), said electronic control unit incorporating a memory (51) in which at least one range of travel of the element has been pre-recorded, and said method comprising a step for the relative modification of the magnitude of at least one range.

Method for configuring an actuator (2) for the operation of a moving element (3) for closure, solar protection, privacy or screening, said actuator comprising a gear motor (4) and a gear motor electronic control unit (5), said electronic control unit incorporating a memory (51) in which at least one range of travel of the element has been pre-recorded, and said method comprising a step for the relative modification of the magnitude of at least one range.

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

An overall machine operational state (such as a problem state, field state, machine state, other non-problem state, etc.) is identified, and exit and entry conditions are monitored to determine whether the machine transitions into another operational state. When the machine transitions into a problem state, a multiple input, multiple output control system uses a state machine to identify the problem state and a solution is identified. The solution is indicative of machine settings that will return the machine to an acceptable, operational state. Control signals are generated to modify the machine settings based on the identified solution.

Exemplary embodiments pertain to a system that can include a high-level controller coupled to a low-level controller for controlling a physical asset. In one exemplary implementation, the high-level controller executes a first finite state machine for controlling a power generation unit via a network. The low-level controller executes a second finite state machine that may have fewer states than the first finite state machine. The second finite state machine places the low-level controller in a default mode of operation for controlling the power generation unit under various conditions such as when the high-level controller is controlling the physical asset during a normal mode of operation; when the high-level controller is revising the first finite state machine; when the high-level controller is controlling the physical asset using a revised first finite state machine; and/or upon detecting a loss of communications between the high-level controller and the low-level controller.

Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuitry on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.