A microcontroller powered by a power management integrated circuit (PMIC) includes a plurality of cores. A first core of the microcontroller can be configured to implement a system power transient management component. One or more other or second cores of the microcontroller can be configured to implement one or more applications. The system power transient management component implemented by the first core can be configured to dynamically identify an expected load transient event to occur in the microcontroller, determine power control data to optimize a response to the identified expected load transient event, the power control data comprising a power control mode and associated parameters, and provide the power control data to the power management integrated circuit (PMIC).

A microcontroller powered by a power management integrated circuit (PMIC) includes a plurality of cores. A first core of the microcontroller can be configured to implement a system power transient management component. One or more other or second cores of the microcontroller can be configured to implement one or more applications. The system power transient management component implemented by the first core can be configured to dynamically identify an expected load transient event to occur in the microcontroller, determine power control data to optimize a response to the identified expected load transient event, the power control data comprising a power control mode and associated parameters, and provide the power control data to the power management integrated circuit (PMIC).

An AC/DC converter includes a first terminal and a second terminal to receive an AC voltage and a third terminal and a fourth terminal to deliver a DC voltage. A rectifying bridge is provided in the converter. A controllable switching or rectifying element has a control terminal configured to receive a control current. A first switch is coupled between a supply voltage and the control terminal to inject the control current. A second switch is coupled between the control terminal and a reference voltage to extract the control current. The first and second switches are selectively actuated by a control circuit.

A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network inlcuding a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.

An AC/DC converter includes a first terminal and a second terminal to receive an AC voltage and a third terminal and a fourth terminal to deliver a DC voltage. A rectifying bridge is provided in the converter. A controllable switching or rectifying element has a control terminal configured to receive a control current. A first switch is coupled between a supply voltage and the control terminal to inject the control current. A second switch is coupled between the control terminal and a reference voltage to extract the control current. The first and second switches are selectively actuated by a control circuit.

An AC/DC converter includes a first terminal and a second terminal to receive an AC voltage and a third terminal and a fourth terminal to deliver a DC voltage. A rectifying bridge is provided in the converter. A controllable switching or rectifying element has a control terminal configured to receive a control current. A first switch is coupled between a supply voltage and the control terminal to inject the control current. A second switch is coupled between the control terminal and a reference voltage to extract the control current. The first and second switches are selectively actuated by a control circuit.

A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network including a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.

An electronic assembly and method for operating the electronic assembly for an automation system, wherein the electronic assembly includes an electronic channel or a plurality of electronic channels and at least one control unit, where an electronic channel has, in each case, a voltage input for applying an input voltage to the electronic channel, a voltage output for tapping off an output voltage at the electronic channel and a buck converter that converts the input voltage applied to the voltage input to the output voltage that has a lower absolute value, and where the method includes applying an input voltage to the voltage input of at least one electronic channel and controlling the buck converter via the control unit such that a signal in accordance with the HART standard can be tapped off at the at least one electronic channel using the output voltage.