An integrated state vector management system for control systems includes a plurality of co-processors configured to generate and utilize state vector data. The integrated state vector management system further includes state vector module communicatively connected to each of the plurality of co-processors. The state vector module includes a state vector memory containing at least three memory buffers for storing three datasets of state vector data. The state vector module further includes a state vector memory control logic communicatively coupled to the state vector memory. The state vector control logic is configured to provide read and write control to the state vector memory. The state vector memory control logic includes at least a write pointer controller and a read pointer controller.

A control system CPU card includes a control CPU chip having a first core and a second core, and a main memory for storing information. A standby system CPU card includes a standby CPU chip having a first core and a second core, and a main memory for storing information. An I/F performs communication to allow the CPU cards to share the information. In the control system CPU card, when the first core is normal, the first core performs control calculation and outputs a calculation result. When the first core is abnormal, the second core is switched to a control core, to perform control calculation and continue output of a calculation result. When the cores are both abnormal, system switching is performed from the control system CPU card to the standby system CPU card.