An analog front end circuit with pulse width modulation current compensation comprises sensing a current condition and determining if the current condition is a positive or negative current condition. An appropriate control signal is determined according to the current condition and sent to turn on a positive current electronic switch if the current condition is a negative current condition or sent to turn on a negative current electronic switch if the current condition is a positive current condition. A positive compensation current flows to offset negative parasitic current when the positive current electronic switch is turned on and a negative compensation current flows to offset positive parasitic current when the negative current electronic switch is turned on. A master control unit utilizes pulse width modulation signals of various widths associated with various current conditions to be sent to turn on the positive electronic switch or the negative electronic switch.

Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

A voltage regulator comprising an error amplifier, a pass transistor and a buffer circuit arranged between the error amplifier and the pass transistor. The buffer circuit comprises a load detector configured to detect a load current of the regulator by monitoring an output signal of the error amplifier. The buffer circuit further comprises a load compensator configured to receive a load signal from the load detector. The load signal indicates the load of the regulator. The load compensator is further configured to change its output impedance based on the load signal such that variations of the load of the voltage regulator are compensated. There is additionally provided a corresponding system, a corresponding method and a corresponding design structure.

Systems, methods, circuits and computer-readable mediums for regulators, e.g., low-dropout (LDO) regulators, with load-insensitive compensations are provided. An example regulator includes an amplifier operable to receive an input voltage and a feedback voltage, a follower responsive to an output voltage of the amplifier and operable to supply a regulated voltage to a load coupled to the follower, and a feedback circuit coupled to the load and the amplifier and operable to provide the feedback voltage. The amplifier is operable to have a substantially unity gain beyond a resonant frequency of the amplifier.

A memory device comprises memory cells, a first regulator, a second regulator, a first switch, a second switch and capacitor coupling switches. The first regulator comprises a first capacitor, and generates a first voltage at a first node connected to a first subset of the memory cells, to provide the first voltage to the first subset. The second regulator comprises a second capacitor, and generates a second voltage at a second node. The first switch selectively couples the second node to a second subset of the memory cells, to provide the second voltage to the second subset. The second switch selectively couples the first node to the second subset to also provide the first voltage to the second subset. The capacitor coupling switches selectively couple the second capacitor in parallel to the first capacitor when the first switch is deactivated, and the second switch is activated.

Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.

An amplifier circuit includes an amplifier, a resistor, and an adaptive bias circuit. The amplifier includes an output and a tail input. The amplifier is configured to generate an output signal representative of a difference of a first input signal and a second input signal. The resistor is coupled to the output of the amplifier. The resistor is configured to lower an output resistance of the amplifier. The adaptive bias circuit is coupled between the output of the amplifier and the tail input of the amplifier. The adaptive bias circuit is configured to generate a detection current based on the output signal, and provide the detection current to the tail input of the amplifier to increase the gain of the amplifier based on the output signal.

In accordance with an embodiment, a method includes receiving an enable signal. After the enable signal is asserted, it is determined whether a soft-start capacitor is electrically connected to an input of a ramp generator circuit while keeping an output of the ramp generator circuit low. If the soft-start capacitor is electrically connected to the input of the ramp generator circuit, a first current is injected into the input of the ramp generator circuit to generate a first voltage ramp at the output of the ramp generator circuit. If the soft-start capacitor is not electrically connected to the input of the ramp generator circuit, a second current is injected to the input of the ramp generator circuit to generate a second voltage ramp at the output of the ramp generator circuit. The second current is smaller than the first current.

A band-gap reference circuit including: mirror current branch circuits, band-gap paths, and an operational amplifier. Each mirror current branch circuit includes a mirror PMOS transistor and an auxiliary PMOS transistor. A drain of each mirror PMOS transistor is connected with a source of a corresponding auxiliary PMOS transistor, and a drain of said each auxiliary PMOS transistor is connected to a top end of a corresponding band-gap path, each gate of each mirror PMOS transistor is connected with an output port of the operational amplifier. A gate of each auxiliary PMOS transistor is connected to a first bias voltage. A substrate electrode of each mirror and auxiliary transistor is all connected to a source voltage. The output port of the operational amplifier outputs a high level less than the source voltage, the first bias voltage is less than an output voltage signal of the operational amplifier.

Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.