A power regulator is applied to regulate a work frequency of a central processing unit and the power regulator comprises a power resister, a voltage amplifier and an analog-to-digital converter. The power resister is coupled to a load to generate a first voltage. The voltage amplifier is coupled to the power resister to output a second voltage. The analog-to-digital converter is coupled to the voltage amplifier, converts the second voltage into a control signal and transmits the control signal to the central processing unit. The control signal is switched between a first level and a second level according to a value of the second voltage.

A simultaneous low quiescent current and high performance low dropout (LDO) voltage regulator is disclosed. In some implementations, the LDO voltage regulator includes a first and a second pass transistors configured to receive an input voltage (Vin). The LDO voltage regulator further includes an error amplifying module having a first output, a second output, a first input, and a second input. The error amplifying module can further include a first output stage configured to drive the gate of the first pass transistor during a high performance (HP) mode, and a second output stage configured to drive the gate of the second pass transistor during the HP mode and during a low power (LP) mode.

A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

An analog circuit arrangement (1) to variably set a voltage U.sub.out, within defined voltage limits, has a non-inverting adder (10) with a positive input (11). A voltage divider (20), with at least a first stage (21) and a second stage (22), is connected to the positive input (11) of the adder (10). At least one stage has a parallel circuit of n resistors (R1, R2, . . . , Rn) that are each connected in series in a conduction path (L1, L2, . . . , Ln) to an overcurrent protection device (F1, F2, . . . , Fn). At least one device (30) actively changes one or more of the overcurrent protection devices (F1, F2, . . . , Fn) into a state that interrupts the respective affected conduction path (L1, L2, . . . , Ln).

A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

A power control semiconductor device includes: a voltage control transistor connected between an input terminal and an output terminal; a control circuit that controls the voltage control transistor in accordance with a voltage of the output terminal; and an external terminal that controls an output voltage externally. The control circuit includes: a first divider which has resistor elements connected in series to the output terminal and which divides the output voltage of the output terminal; a first error amplifier that outputs a voltage corresponding to a potential difference between a predetermined reference voltage and a voltage divided by the first divider; and an output voltage change circuit that changes the divided voltage in accordance with a voltage input to the external terminal to change the output voltage in accordance with the voltage of the external terminal.

A voltage generation circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generation circuit also includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of the bias current may be forcibly adjusted by the control signal.

A power supply control apparatus includes a voltage control transistor connected between a DC voltage input terminal and an output terminal; a control circuit which controls the voltage control transistor according to an output feedback voltage; and a first external terminal receiving an output control signal to control an output voltage. The control circuit includes a first error amplifier outputting a voltage according to an electric potential difference between a voltage divided by a first voltage dividing circuit which divides the output voltage of the output terminal and a predetermined reference voltage; and an output changing circuit including a second error amplifier receiving a voltage input in the first external terminal, a transistor having a control terminal receiving the output of the second error amplifier, and a current mirror circuit connected to the voltage input terminal which transfers an electric current flowing in the transistor. The current mirror circuit is connected to a node from which the divided voltage is taken out, and the output changing circuit displaces the divided voltage according to a voltage input in the first external terminal to change the output voltage according to the output control signal.

The voltage regulator comprises: a voltage regulation circuit, a detection circuit and at least one current source unit. An output terminal of the voltage regulation circuit is electrically connected to a first terminal of each of the current source units, and is configured to be electrically connected to a load; and a second terminal of each of the current source units is electrically connected to a first voltage terminal. The detection circuit is electrically connected to the voltage regulation circuit, and is configured to: when the voltage regulation circuit is in a light-load state, control a designed number of the current source units to connect to the output terminal of the voltage regulation circuit to output designed current, and when the voltage regulation circuit is in a heavy-load state, control each of the current source units to disconnect from the output terminal of the voltage regulation circuit.

In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.