A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.

A termination voltage regulation apparatus with transient response enhancement includes a termination voltage regulator and a transient response enhancer. The termination voltage regulator provides a termination voltage at a termination voltage terminal, including first and second switching units. The transient response enhancer, coupled to the termination voltage regulator, is utilized for enhancing transient response of the termination voltage regulator, including a first enhancement circuit for sensing a first signal associated with the first switching unit and enabling a first control terminal of the first switching unit to be at a first voltage in response to the first signal in a sinking mode; and a second enhancement circuit for sensing a second signal associated with the second switching unit and enabling a second control terminal of the second switching unit to be at a second voltage in response to the second signal in a sourcing mode.

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

An apparatus may include a transient voltage suppression (TVS) device array coupled to a first input terminal and a second input terminal; and a linear regulator module having a pair of inputs connected to a respective pair of outputs of the TVS device array, wherein the TVS device array includes at least one TVS diode is connected between a first output and second output of the pair of outputs to generate a first clamping voltage signal, and wherein the linear regulator module is configured to generate a second clamping voltage signal having a second clamping voltage independent of a first clamping voltage of the first clamping voltage signal received from the TVS device array.

An apparatus may include a transient voltage suppression (TVS) device array coupled to a first input terminal and a second input terminal; and a linear regulator module having a pair of inputs connected to a respective pair of outputs of the TVS device array, wherein the TVS device array includes at least one TVS diode is connected between a first output and second output of the pair of outputs to generate a first clamping voltage signal, and wherein the linear regulator module is configured to generate a second clamping voltage signal having a second clamping voltage independent of a first clamping voltage of the first clamping voltage signal received from the TVS device array.

A converter assembly including a source connection system including a primary source connection, and a plurality of secondary source connections, a load connection system including a load connection, a secondary source bus bar system, a switch system including a plurality of switch units each connected electrically between a corresponding secondary source connection and the secondary source bus bar system, and at least one converter module including a DC link and a secondary source side converter. Each switch unit of the switch system includes a first switch and a second switch connected in parallel, wherein the first switch has a higher switching speed than the second switch, and the second switch has a lower conduction losses than the first switch.

A converter assembly including a source connection system including a primary source connection, and a plurality of secondary source connections, a load connection system including a load connection, a secondary source bus bar system, a switch system including a plurality of switch units each connected electrically between a corresponding secondary source connection and the secondary source bus bar system, and at least one converter module including a DC link and a secondary source side converter. Each switch unit of the switch system includes a first switch and a second switch connected in parallel, wherein the first switch has a higher switching speed than the second switch, and the second switch has a lower conduction losses than the first switch.

An output circuit includes: a first p-type transistor having a source connected to VDDH and a gate to which an input signal is fed; and a second p-type transistor having a source connected to the drain of the first p-type transistor, a drain connected to an output terminal, and a gate connected to a first node. A capacitor has one terminal to which the input signal is fed and the other terminal connected to the first node. A first n-type transistor has a source connected to VDDL, a drain connected to the first node, and a gate to which a signal corresponding to the input signal is fed. A second n-type transistor has a source and a gate both connected to VDDL and a drain connected to the first node.

An output circuit includes: a first p-type transistor having a source connected to VDDH and a gate to which an input signal is fed; and a second p-type transistor having a source connected to the drain of the first p-type transistor, a drain connected to an output terminal, and a gate connected to a first node. A capacitor has one terminal to which the input signal is fed and the other terminal connected to the first node. A first n-type transistor has a source connected to VDDL, a drain connected to the first node, and a gate to which a signal corresponding to the input signal is fed. A second n-type transistor has a source and a gate both connected to VDDL and a drain connected to the first node.

Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.