Systems and components for use with neural networks. An execution block and a system architecture using that execution block are disclosed. The execution block uses a fully connected stack of layers and one output is a forecast for a time series while another output is a backcast that can be used to determine a residual from the input to the execution block. The execution block uses a waveform generator sub-unit whose parameters can be judiciously selected to thereby constrain the possible set of waveforms generated. By doing so, the execution block specializes its function. The system using the execution block has been shown to be better than the state of the art in providing solutions to the time series problem.

A method and apparatus for generating an RF signal uses digital signal components to generate a synthesized RF signal having a plurality of frequency components. An analog filter is used to filter the synthesized RF signal. The analog filter is a tunable, active feedback circuit having one or more variable resonators and a variable gain block connected in a signal loop that is defined by a passband. The analog filter is tuned such that the passband of the analog filter overlaps one or more desired frequency components of the plurality of frequency components of the synthesized RF signal, and such that the passband has a relative bandwidth of about 1% or less.

The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.

An arbitrary waveform sequencer device for playing a list of at least a first and a second arbitrary waveform file in a sequence is provided. The arbitrary waveform sequencer device comprises a list increment condition control unit configured to control an increment from the first to the second arbitrary waveform file as a function of an increment condition, and a transition control unit configured to control a timing of the increment.

A designed waveform generator includes at least one first signal generator including a first switching device and generating a square wave having a constant voltage level during an on-period of the first switching device and at least one second signal generator including a second switching device and controlling a transition period of the second switching device to generate a variable waveform having a variable voltage level during the transition period of the second switching device. The at least one first signal generator and the at least one second signal generator are connected to each other in a cascade manner.

The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

The disclosed embodiments relate to a system that compactly stores time-series sensor signals. During operation, the system receives original time-series signals comprising sequences of observations obtained from sensors in a monitored system. Next, the system formulizes the original time-series sensor signals to produce a set of equations, which can be used to generate synthetic time-series signals having the same correlation structure and the same stochastic properties as the original time-series signals. Finally, the system stores the formulized time-series sensor signals in place of the original time-series sensor signals.

The present invention provides an arbitrary waveform generator based on instruction architecture. To deal with the feature that the instructions and waveform data of the AWG are coupled in the prior art, an instruction set based waveform synthesis controller is employed, and substitutes for the sequence wave generator in the present invention, i.e. an arbitrary waveform generator based on instruction architecture. Thus the time-sharing scheduling in reading the waveform synthesis instruction and the segment waveform data is realized, and the complexity of the hardware is reduced, so that the AWG in present invention can synthesize and generate a complex sequence wave rapidly and efficiently.

An aspect includes a direct digital synthesis system including a waveform generator with a waveform memory operable to store a plurality of waveform vectors and output a selected waveform vector. The direct digital synthesis system also includes a digital-to-analog converter operable to convert the selected waveform vector from a digital value to an analog signal responsive to a reference clock. The direct digital synthesis system further includes a controller operable to maintain phase continuity of the analog signal when an output of the analog signal is interrupted and restored.