G06F3/0628

System, method, and computer program product for conditionally eliminating a memory read request

A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.

Storage system, storage control device, and method of controlling a storage system
10528275 · 2020-01-07 · ·

A storage system includes a first storage control device including a first memory being a volatile memory and a first processor, and a second storage control device including a second memory being a non-volatile memory and a second processor, wherein the second processor is configured to receive a first write request to write first data into a first storage device, store the first data into the second memory, and transmit the first data to the first storage control device, the first processor is configured to store the first data into the first memory, and transmit a first notification to the second storage control device, and the second processor is configured to receive the first notification, transmit a first completion notification in response to the first write request, and execute processing to write the first data, stored in the second memory, into the first storage device.

OUT-OF-BAND UPDATING METHOD AND SYSTEM OF EXPANDER

An out-of-band updating method and system of an Expander, applied to a controller connected to the expander by means of a communication bus. The method comprises: receiving firmware updating data sent by a user (S101); fragmenting the firmware updating data (S102); and only when determining that the expander is in an idle state, sending the fragmented data until each piece of data is sent to the Expander, such that the expander completely receiving the firmware updating data completes updating by restarting (S103). The data transmission speed is facilitated to be improved, the normal operation of a service is ensured, and the conditions of influencing state monitoring and log loss are avoided.

Pipelined decompression of sliding window compressed data

Decompressing sliding window compressed data requires reference to previously decompressed character sequences. Previously decompressed data is stored in a history buffer to satisfy these back references. As each decompressed/decoded character is emitted, it is stored in this history buffer. Thus, for each decompressed character that is emitted, the history buffer may need to be accessed at least twiceonce to retrieve the backreference, and once to store the emitted character. A pipeline architecture is disclosed that stores decompressed characters in a write queue that coalesces eight or more emitted characters before they are stored in the history buffer memory. This reduces collisions between accessing the history buffer memory to retrieve the backreferences and the storing of the emitted character. This also allows the use of a single-ported memory which is less expensive than a multi-ported memory.

Adaptive quality of service control circuit
10481944 · 2019-11-19 · ·

Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

Data compression system for storing data from an automated vehicle

A data-compression system for compressing and storing sampled data from an electronic control unit (ECU) in an automated vehicle includes an input and a controller. The input receives and samples a signal during a time-interval to provide a frame of sampled-data. The controller is in communication with the input. The controller is configured to capture the frame of sampled-data; determine an average-value of the sampled-data in the frame, and convert the sampled-data to percentage-data using the average-value as the basis for the conversion.

Out-of-band updating method and system of expander

An out-of-band updating method and system of an Expander, applied to a controller connected to the expander by means of a communication bus. The method comprises: receiving firmware updating data sent by a user (S101); fragmenting the firmware updating data (S102); and only when determining that the expander is in an idle state, sending the fragmented data until each piece of data is sent to the Expander, such that the expander completely receiving the firmware updating data completes updating by restarting (S103). The data transmission speed is facilitated to be improved, the normal operation of a service is ensured, and the conditions of influencing state monitoring and log loss are avoided.

Copy of memory information from a guest transmit descriptor from a free pool and assigned an intermediate state to a tracking data structure

Examples include the copy of memory information from a transmit descriptor to a tracking data structure. Some examples include the memory information being copied from a guest transmit descriptor to a tracking data structure of the guest OS and assignment of the guest transmit descriptor back to a free pool, in response to a determination that the guest transmit descriptor is assigned to an intermediate state.

Data storage device with noise injection

Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

ADAPTIVE QUALITY OF SERVICE CONTROL CIRCUIT
20190050252 · 2019-02-14 · ·

Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.