Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

A data-compression system for compressing and storing sampled data from an electronic control unit (ECU) in an automated vehicle includes an input and a controller. The input receives and samples a signal during a time-interval to provide a frame of sampled-data. The controller is in communication with the input. The controller is configured to capture the frame of sampled-data; determine an average-value of the sampled-data in the frame, and convert the sampled-data to percentage-data using the average-value as the basis for the conversion.

A data storage system implements out-of-order data transfer. In one embodiment, the data storage system can retrieve from a host system a scatter gather list (SGL) associated with a data read command and generate a memory access table based on the retrieved SGL. The data storage system can further retrieve data from memory, and at least some data may be retrieved out of order. Retrieved data can be provided to the host system using the memory access table, and at least some data may be provided out of order. Data retrieval performance can be increased.

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

Resource provisioning to a process in a distributed computing system, such as a cloud computing system. An instruction to provision a resource is received. Portions of the resource are provisioned to the process as they become available, and prior to all portions becoming available, based on determining that the provisioning speed is greater than or equal to the use speed for the resource. If the use speed is faster, it may be actively slowed down.

This disclosure is directed to systems, apparatuses, and methods of storing a data entity using at least two sectors of a memory device based at least in part on context information of the data entity. For example, the context information may differentiate between large sequential operations and small random operations, and may further improve multitasking support. The context information may further improve operations to erase data in the memory device. For example, a method may include storing a data entity using at least two sectors of a memory device, the at least two sectors associated with the same data entity, and maintaining, at a memory controller, context information of the data entity comprising a pointer to at least one of the at least two sectors of the memory device. The method may further include erasing the at least two sectors of the memory device using the context information.

A digital microprocessor device (2) has: a central processing unit; a memory (8); and an output signal module (4). The output signal module comprises: a counter (6) arranged to count to a predetermined count value; and at least one comparator (10a, 10b, 10c) arranged to change an output signal (14a, 14b, 14c) from a first output state to a second output state when the counter reaches a predetermined comparator value. The output signal module is arranged to load automatically from the memory at least one parameter selected from the group comprising: the predetermined count value, the predetermined comparator value and the first output state or the second output state, without receipt of an instruction from the central processing unit.

Resource provisioning to a process in a distributed computing system, such as a cloud computing system. An instruction to provision a resource is received. Portions of the resource are provisioned to the process as they become available, and prior to all portions becoming available, based on determining that the provisioning speed is greater than or equal to the use speed for the resource. If the use speed is faster, it may be actively slowed down.