A system and methods for designing single-stage hardware sorting blocks, and further using the single-stage hardware sorting blocks to reduce the number of stages in multistage sorting processes, or to define multiway merge sorting networks.

A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.

A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.

Methodology to reduce the running time of any string sorting algorithm is described. In one methodology, a prefix of each string from the input unsorted string array is converted to an integer and placed in an array. The array of integers is sorted using the given sorting algorithm. In subsequent methodology, the characters of the string prefix are placed in a record structure and stored in an array of character records. The array of character records is sorted using the given sorting algorithm. The input unsorted array of strings is then sorted using either the sorted array of integers or character records as a reference. Both methodologies showed performance improvements when running in sequential mode only. Therefore, parallel data sort methodology (PDS) was introduced allowing sorting algorithms to sort data in parallel, and its implementation made the two methodologies execute much faster in parallel mode.

Methodology to reduce the running time of any string sorting algorithm is described. In one methodology, a prefix of each string from the input unsorted string array is converted to an integer and placed in an array. The array of integers is sorted using the given sorting algorithm. In subsequent methodology, the characters of the string prefix are placed in a record structure and stored in an array of character records. The array of character records is sorted using the given sorting algorithm. The input unsorted array of strings is then sorted using either the sorted array of integers or character records as a reference. Both methodologies showed performance improvements when running in sequential mode only. Therefore, parallel data sort methodology (PDS) was introduced allowing sorting algorithms to sort data in parallel, and its implementation made the two methodologies execute much faster in parallel mode.

Vectorized sorted-set intersection is performed using conflict-detection single instruction, multiple data (SIMD) instructions. A first ordered subset of values of a first ordered set of distinct values and a second ordered subset of values of a second ordered set of distinct values is loaded into a register. A first value in the register that matches another value in the register (i.e., common values) is identified by performing an SIMD instruction. The first value is then stored in a result set representing a merge-sort result set between the first ordered set of distinct values and the second ordered set of distinct values.

Vectorized sorted-set intersection is performed using conflict-detection single instruction, multiple data (SIMD) instructions. A first ordered subset of values of a first ordered set of distinct values and a second ordered subset of values of a second ordered set of distinct values is loaded into a register. A first value in the register that matches another value in the register (i.e., common values) is identified by performing an SIMD instruction. The first value is then stored in a result set representing a merge-sort result set between the first ordered set of distinct values and the second ordered set of distinct values.

A query processing device includes a communication interface accessing a database and database catalog, a memory storing instructions, and a processor coupled to the memory and the communication interface. The processor executes the instructions to parse a query and generate first and second execution plans for the query, retrieve respective previously determined cardinality values for previously executed logical steps of the first and second execution plans from the database catalog, select an execution plan from the first execution plan or the second execution plan, the selected execution plan having a lower cost based on the previously determined cardinality values, and execute the selected execution plan on data accessed from the database. The query processing system stores actual cardinality values determined during the execution of the logical steps in the database catalog for use by subsequent queries. The query processing device, therefore, re-uses previously determined cardinality values.

The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.

The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.