A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

A MAC tag list generation apparatus, on reception of a nonce N unique value to each MAC generation process and a message M, generates a t×m group test matrix H serving as combinatorial group testing parameters for s (a positive integer) which is the number of the MACs to be generated, generates a MAC tag list T=(T[1], . . . , T[t]) by generating a MAC value T[i] corresponding to the i-th test (i=1, . . . , t) using the group test matrix H, the nonce N, and pseudorandom functions F and G with variable length input and fixed length output for the message M, and outputs the MAC tag list.

A computer-implemented method, and system, for detecting modification of a semiconductor device includes generating and applying an exhaustive first set of patterns to a netlist golden model of a golden device. The exhaustive first set of patterns is developed by a pseudorandom number generator. Applying the patterns to stimulate the device produces a first response serial bit stream in relation to logical composition of the golden model. A signature analyzer compresses the total output to provide a first cyclic redundancy code or answer. The same exhaustive set of patterns can be provided to stimulate the model of an unknown device. The unknown device is shown to be identical to the golden device if its answer matches that of the golden device and modified if its answer does not match that of the golden device.

According to this disclosure, a method of synthesizing an audio stream sample using a processor is provided. The method comprises: generating a set of unnormalized log probabilities using a neural network, each unnormalized log probability associated with a possible value for the audio stream sample, sampling a Gumbel distribution for each of the unnormalized log probabilities, adding the samples from the Gumbel distribution to each of the respective unnormalized log probabilities to generate a set of modified log probabilities, each modified log probability associated with a possible value for the audio stream sample, and selecting the possible value of the audio stream sample associated with the largest modified log probability from the set of modified log probabilities as the audio stream sample.

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations by updating a cryptographic state. The methods and systems may be used to provide cryptographic functions such as hashing, encryption, decryption and random number generation. In one example, a non-linear feedback shift register or expander sequence is defined. The non-linear feedback shift register or expander sequence has a plurality of stages to receive the cryptographic state, wherein at least one of the plurality of stages is updated as a non-linear function of one or more other stages. In certain examples, a cryptographic state is updated over a plurality of rounds. Examples adapted for authenticated encryption and decryption, hashing, and number generation are described.

A structure for generating sequences. The structure includes a binary shift register; a feedback structure connected to the shift register arranged to define a linear feedback shift register according to a polynomial; a first output arranged to collect one or more state values from a first group of elements of the shift register, the one or more state values from the first group forming a value of a first sequence; and a second output arranged to collect one or more state values from a second group of elements of the shift register, the one or more state values from the second group forming a value of a second sequence. No element of the second group belongs to the first group.

Embodiments comprise construction of a collection of pseudorandom number generators (PRNGs), with either a known or unknown cardinality, using unique brine values that comprise a salt value for the collection and also different index values for each PRNG for the collection. The additive parameters of such PRNGs are based on the respective brine values of the PRNGs, thereby ensuring that the PRNGs in the collection have different state cycles. Embodiments make it likely that PRNGs from different collections have distinct additive parameters by choosing a pseudorandom salt value for each collection. According to embodiments, a stream of generators in a collection is created by a spliterator that carries a salt value for the collection and combines the salt value with index values for the generators to produce brined additive parameters for the PRNGs in the stream. According to embodiments, such a stream may be executed by multiple threads in parallel.

A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.

A shared bus for inter-channel communication comprising two or more channels having signal processing elements such that each channel is configured to receive and process an incoming channel specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of a channel. An error checker is configured to error check incoming channel specific signals. A shared bus connects to the two or more channels to communicate an incoming channel specific signal to the error checker and communicate the test sequence to the signal processing elements of a channel. One or more pull up resistors and/or termination resistors connect to the shared bus. The bus may comprise a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The bus interface comprises an open collector current mode logic driver in cascode arrangement.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.