Apparatus and method for generating true random numbers for an integrated circuit, wherein the method includes providing a counter in an integrated circuit that counter receives a clock signal of the integrated circuit, sending the signal of a resistor-capacitor circuit that act as an oscillator to the counter, where the resistor-capacitor circuit is situated outside the integrated circuit and is connected to the integrated circuit via input/output pins, changing the signal of the resistor-capacitor circuit by randomly switching one or more additional resistors in parallel to the resistor of the resistor-capacitor circuit to change the frequency of the signal of the resistor-capacitor circuit and counting the oscillations of the clock during one oscillation of the signal of the resistor-capacitor circuit and filling a register with the resulting bit stream.

A structure for generating sequences. The structure includes a binary shift register; a feedback structure connected to the shift register arranged to define a linear feedback shift register according to a polynomial; a first output arranged to collect one or more state values from a first group of elements of the shift register, the one or more state values from the first group forming a value of a first sequence; and a second output arranged to collect one or more state values from a second group of elements of the shift register, the one or more state values from the second group forming a value of a second sequence. No element of the second group belongs to the first group.

A random number generating circuit includes M random number generators, where M is an integer greater than or equal to 2, configured to be independent of each other and generate M random number sequences, a delay adjustment circuit configured to output N sets of the M random number sequences including N different relative time differences or N different combinations of a plurality of relative time differences, where N is an integer greater than or equal to 2, by adjusting one or more relative time differences between the M random number sequences, and a logic operation circuit configured to perform an exclusive OR operation between the M random number sequences included in a set, for each of the N sets of the M random number sequences.

In one embodiment, a microprocessor, comprising: prediction logic comprising a branch predictor comprising a group of multi-set associative tables, each of the tables corresponding to branch pattern histories of different lengths; and control logic configured to provide an adjustable write policy for the prediction logic.

A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.

Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

An apparatus includes a processor to generate a random exponent having a fixed bit width, divide the random exponent into a pre-exponent portion and a post-exponent portion at a random bit position in the fixed bit width, and generate a cryptographic key using the pre-exponent portion and the post exponent portion

A pseudo-random number generation circuit device includes a pseudo-random number generation circuit including a logic circuit configured based on rule data that generates a next random number value from a current random number value, a cycle detection circuit that detects, based on a seed, an end of a cycle of random numbers, which are generated by the pseudo-random number generation circuit, and a rule data generation circuit that generates new rule data at a first trigger, at which the cycle detection circuit detects the end of the cycle of random numbers, to output the new rule data to the pseudo-random number generation circuit, wherein the cycle detection circuit stores a random number value, which is generated by a new logic circuit configured based on the new rule data, as the seed.

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations by updating a cryptographic state. The methods and systems may be used to provide cryptographic functions such as hashing, encryption, decryption and random number generation. In one example, a non-linear feedback shift register or expander sequence is defined. The non-linear feedback shift register or expander sequence has a plurality of stages to receive the cryptographic state, wherein at least one of the plurality of stages is updated as a non-linear function of one or more other stages. In certain examples, a cryptographic state is updated over a plurality of rounds. Examples adapted for authenticated encryption and decryption, hashing, and number generation are described.