Patent classifications
G06F7/586
METHOD FOR THE MANAGEMENT OF VIRTUAL OBJECTS CORRESPONDING TO REAL OBJECTS, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT
A method for managing virtual objects (O) corresponding to real objects (R), said virtual objects (O) comprising a set (OP) of information or data representing said real object (R), said virtual objects (0) residing in a management system (20), which comprises a computer system (21) accessible by user terminals (13) through a telecommunication network to enable operations to be carried out on said virtual objects (O) in a database (22a) in said computer system (21), said method comprising the operations of: generating (100), in response to a request of a requesting subject (C) to create one or more virtual objects (O) that represent respective real objects (R), corresponding unique identifier codes (Z, z.sub.x, c, i) that enable a user terminal (13) to carry out operations on the respective virtual object (O). According to the invention, said unique identifier codes (z.sub.x, c, i) enable a user terminal (13) to carry out a procedure of activation of the respective virtual object (O) by associating in the database (22a) comprised in said computer system (21) a unique identifier code (Z, (Z, z.sub.x, c, i) to a first basic set (BP) of information supplied by said owning subject (C) at the moment of the request, said identifier code (z.sub.x, c, i) being calculated on the basis of: a first value (X) identifying a class to which the virtual object belongs (O); a second value (C) identifying said requesting subject; and a third value (i) representing a label that identifies said virtual object (0) in said class (X).
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDATION
Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.
Apparatus and method for unbreakable data encryption
An encryption specification named “MetaEncrypt” implemented as a method and associated apparatus is disclosed for unbreakable encryption of data, code, applications, and other information that uses a symmetric key for encryption/decryption and to configure the underlying encryption algorithms being utilized to increase the difficulty of mathematically modeling the algorithms without possession of the key. Data from the key is utilized to select several encryption algorithms utilized by MetaEncrypt and configure the algorithms during the encryption process in which block sizes are varied and the encryption technique that is applied is varied for each block. Rather than utilizing a fixed key of predetermined length, the key in MetaEncrypt can be any length so both the key length and key content are unknown. MetaEncrypt's utilization of key data makes it impossible to model its encryption methodology to thereby frustrate cryptographic cracking and force would be hackers to utilize brute force methods to try to guess or otherwise determine the key.
Parallelization of random number generators
System and method for pseudo-random number generation based on a recursion with significantly increased multithreaded parallelism. A single pseudo-random generator program is assigned with multiple threads to process in parallel. N state elements indexed incrementally are arranged into a matrix comprising x rows, where a respective adjacent pair of state elements in a same column are related by g=(M+j)mod N, wherein j and g represent indexes of the pair of state elements. x can be determined through an modular manipulative inverse of M and N. The matrix can be divided into sections with each section having a number of columns, and each thread is assigned with a section. In this manner, the majority of the requisite interactions among the state elements occur without expensive inter-thread communications, and further each thread may only need to communicate with a single other thread for a small number of times.
Method of generating uniform and independent random numbers
For any multiplicative congruential generator (d, z) with an odd modulus d and a multiplier z coprime to d, a computationally innovative method is presented as specialized forms of 2nd degree spectral tests of (d, z^i) with 2≦i≦6, at the least. Providing with sharp and powerful sieving tools, the method enables the excavation of the integer set (d, z) as a generator of uniform and independent random numbers of excellent statistics with sufficiently long periods for simulations, and furnishes the selected generator with ways of clear, unambiguous and quantitative specifications of its performance.
Generating integers for cryptographic protocols
In a general aspect, pseudorandom integers are generated for use in a cryptographic protocol. In some aspects, a first plurality of digits are obtained and converted to a second plurality of digits. The first plurality of digits (e.g., bits) represent an integer in a first number system (e.g., binary), and the second plurality of digits (e.g., trits) represent the integer in a second number system (e.g., trinary). A plurality of integers in the first number system are generated based on the second plurality of digits, and an array of integers is produced. Each integer in the array is less than a modulus, and the array includes the plurality of integers. The array of integers can be used in a lattice-based cryptographic protocol.
Extended reality authentication
Methods and systems for secure authentication in an extended reality (XR) environment are described herein. An XR environment may be output by a computing device and for display on a device configured to be worn by a user. A first plurality of images may be determined via the XR environment. The first plurality of images may be determined based on a user looking at a plurality of objects, real or virtual, in the XR environment. The first plurality of images may be sent to a server, and the server may return a second plurality of images. A public key and private key may be determined based on different portions of each of the second plurality of images. The public key may be sent to the server to register and/or authenticate subsequent communications between the computing device and the server.
Automated vehicle lane positioning
A vehicle lane positioning system includes a sensor arrangement that is designed to determine lateral boundaries of a vehicle lane. A control unit is designed to calculate a vehicle travel path within the vehicle lane having a predetermined variation from a centered vehicle pathway. An actuator unit is designed to execute the vehicle travel path within the vehicle lane.
SYSTEM AND METHOD FOR DISTRIBUTED LAPLACE NOISE GENERATION FOR DIFFERENTIAL PRIVACY
A computer-implemented method includes generating shared random bits at the two or more nodes in a multi-party computation system, obtaining one or more Gaussian samples at the two or more modes utilizing the shared random bits, at each of the two or more nodes, generate and output one or more Laplacian samples using the one or more Gaussian samples.
Validation of store coherence relative to page translation invalidation
Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.