An electronic random number generating device (100) for generating a sequence of random numbers, the electronic random number generating device comprising an electronic parameter storage (110) configured to store multiple functions and for each function of the multiple functions an associated modulus, not all moduli being equal, and an electronic function evaluation device (120) configured to generate an internal sequence of random numbers, the function evaluation device being configured to generate a next number in the internal sequence of random numbers by for each function of the multiple functions, evaluating the function for a previously generated value in the internal sequence of random numbers modulo the modulus associated with the evaluating function, so obtaining multiple evaluation results, and applying a combination function to the multiple evaluation results to obtain the next number in the internal sequence, and an output (140) configured to generate a next number in the sequence of random numbers from the generated next number in the internal sequence.

Various examples of the present disclosure relate to apparatuses, methods, computer systems and computer-readable media for generating and using random values. Some aspects of the present disclosure relate to an apparatus for a computer system, the apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to determine different canary values for corresponding different threads of a program, and start the thread of the program, with the determined canary value being used as stack canary for the thread of the program.

A random number generator includes: a random number generating circuit used for generating a pulse signal based on a control word and generating a random number signal according to the pulse signal, the pulse signal including a first frequency signal and a second frequency signal that appear alternately, and proportions of the first frequency signal and the second frequency signal being controlled by the control word; and a feedback update circuit used for updating the control word based on the random number signal output by the random number generating circuit.

An improved pseudo-random number generator is introduced that has increased security due to higher randomness and lower predictability. The PRNG uses seed values that are based on a combination of various selectable values from the real-world that are typically made publicly available over a computer network (i.e., the Internet), such as: one or more weather conditions at a particular time or date and geographic location, a score of a sports event, a stock market index or ticker value, an election vote total, attendance at a cultural event, gross dollar sales from a movie release, and other such numerically quantifiable values that, individually and in combination, are impossible to exactly predict in advance, yet are precisely verifiable after the number-generating event using electronically-stored information. The improved pseudo-random number generator may be used for more secure determination of lottery outcomes and the like.

A system comprises a receiver comprising a first pseudorandom binary sequence module, and a transmitter comprising a second pseudorandom binary sequence module. The first pseudorandom binary sequence module is initialized with a first received bit sequence to start bit sequence generation with the aid of the second pseudorandom binary sequence module. Further, received remaining bits are compared to bit sequences generated with the aid of the first pseudorandom binary sequence module to determine whether a bit error rate is below a predefined threshold.

A system comprises a receiver comprising a first pseudorandom binary sequence module, and a transmitter comprising a second pseudorandom binary sequence module. The first pseudorandom binary sequence module is initialized with a first received bit sequence to start bit sequence generation with the aid of the second pseudorandom binary sequence module. Further, received remaining bits are compared to bit sequences generated with the aid of the first pseudorandom binary sequence module to determine whether a bit error rate is below a predefined threshold.

The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein the first data element is divided in N second data elements being stored in the memory, and first data element being equal to the sum, modulo the dimension of a space comprising the first data element, of the N second data elements, wherein an image of the first data element by a LCG function is stored in the memory, and the method comprising a step of checking if the image of the first data element by the LCG function is equal to the sum, modulo the module of the LCG function, of a product of an integer varying from 0 to N?1 and an image of the dimension by the LCG function, and of the images of the second data elements by the LCG function.

A first semiconductor device includes a processor configured to generate a random number at initial test of a second semiconductor device after fabrication of the second semiconductor device in a supply chain related to the second semiconductor device, and send the generated random number to the second semiconductor device. The processor is further configured to receive a first signature that is signed over the sent random number by the second semiconductor device using a first private key that is stored in the second semiconductor device, among a first private and public key pair, and test the received first signature, using a first public key that is stored in the first semiconductor device, among the first private and public key pair, to determine whether the second semiconductor device is authenticated.

A combination of secure texts of values a, b and c having a relationship c=ab is efficiently generated. A secure text generation part 12 generates secure texts [x.sub.i] of x.sub.i satisfying x.sub.i=f(k.sub.i), and secure texts [y.sub.i] of y.sub.i satisfying y.sub.i=g(k.sub.i), for i=0, . . . , m. A fragment generation part 13 generates .sub.i decrypted from [x.sub.i][a.sub.i] and .sub.i decrypted from [y.sub.i][b.sub.i], for i=1, . . . , m, and calculates [c.sub.i]+.sub.i[b.sub.i]+.sub.i[a.sub.i]+.sub.i.sub.i and generates secure texts [z.sub.1], . . . , [z.sub.m]; and A random number synthesizing part 14 generates a secure text [z.sub.0] using different values k.sub.0, . . . , k.sub.m and secure texts [z.sub.1], . . . , [z.sub.m].

Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.