A method and apparatus for detecting and correcting digit errors of arithmetic results and signed data represented in a redundant residue number system (RRNS) and further represented using a non-systematic method of complements suitable for processing by a complement based digital arithmetic of the full redundant range

A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.

Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.

An electronic calculating device (100; 200) arranged to calculate the product of integers, the device comprising a storage (110) configured to store integers (210, 220) in a multi-layer residue number system (RNS) representation, the multi-layer RNS representation having at least an upper layer RNS and a lower layer RNS, the upper layer RNS being a residue number system for a sequence of multiple upper moduli (M.sub.i), the lower layer RNS being a residue number system for a sequence of multiple lower moduli (m.sub.i), an integer (x) being represented in the storage by a sequence of multiple upper residues (x.sub.i=(x).sub.Mi; 211, 221) modulo the sequence of upper moduli (M.sub.i), upper residues (x.sub.j; 210.2, 220.2) for at least one particular upper modulus (M.sub.j) being further-represented in the storage by a sequence of multiple lower residues ((x.sub.j).sub.mj, 212, 222) of the upper residue (x.sub.j) modulo the sequence of lower moduli (m.sub.i), wherein at least one of the multiple lower moduli (m.sub.i) does not divide a modulus of the multiple upper moduli (M.sub.j).

A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

An integrated photonics computing system implements a residue number system (RNS) to achieve orders of magnitude improvements in computational speed per watt over the current state-of-the-art. RNS and nanophotonics have a natural affinity where most operations can be achieved as spatial routing using electrically controlled directional coupler switches, thereby giving rise to an innovative processing-in-network (PIN) paradigm. The system provides a path for attojoule-per-bit efficient and fast electro-optic switching devices, and uses them to develop optical compute engines based on residue arithmetic leading to multi-purpose nanophotonic computing.

An electronic calculating device (100) arranged to perform obfuscated arithmetic in a commutative ring (Z.sub.M; Z.sub.n[x]/M(x)) defined by a combined modulus (M; M(x)) in a residue number system, the residue number system being defined for a series of moduli (m.sub.1, m.sub.2, . . . , m.sub.N), each modulus defining a commutative ring (Z.sub.M1; Z.sub.n[x]/m.sub.1(x)), for each modulus (m.sub.i) of the series there exists an associated base element (u.sub.i) satisfying the condition that each ring element (x.sub.j) modulo the modulus (m.sub.j) may be expressed as an integer-list ((a.sub.j, b.sub.j)) such that the ring elements equal a linear combination of powers of the base element (xj=u.sub.i.sup.aju.sub.i.sup.bj), wherein the powers have exponents determined by the integer-list.

A cryptographical apparatus for converting input bit sequences, whose overflow-free arithmetic addition results in a secret, into output bit sequences whose logic XORing results in the secret. The apparatus comprises a data interface for providing a first input bit sequence and a second input bit sequence and a processing circuit configured to a) gate the first input bit sequence and the second input bit sequence to obtain a logic result indicating overflow bit positions at which both the first input bit sequence and the second input bit sequence have a value of one; and to b) change the first and/or second input bit sequence at at least one overflow bit position. The processing circuit is configured to repeatedly perform steps a) and b) by using the respectively changed input bit sequences, until the logic result indicates no further overflow bit position and the output bit sequences are obtained.

Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.