Techniques for representing a native function using an executable reference are disclosed. The system receives an instruction to create an executable reference for a native function, including a method type comprising a method signature corresponding to the executable reference, and a function description including (a) a memory layout corresponding to data returned by the function and (b) memory layouts corresponding to parameters required by the function. The system selects an application binary interface (ABI). The system generates code that, for each parameter, of the one or more parameters required by the function, converts the parameter from a value formatted for use by a Java Virtual machine to a value formatted for use in the native function, based on the selected ABI. Responsive to invocation of the executable reference, the generated code and the native function may be executed.

A computing device including a processor configured to receive source code including a plurality of source code modules. The processor may generate executable code from the source code and assign two or more reload indicators to two or more executable code modules. The processor may execute the executable code. During execution of the executable code, the processor may receive a source code update and generate an executable code update from the source code and the source code update. The processor may apply the executable code update to the executable code to generate updated executable code. The processor may generate a reload ordering of two or more reload operations corresponding to the reload indicators. As specified by the reload ordering, the processor may perform the two or more reload operations at the two or more respective executable code modules. The processor may execute the updated executable code.

Techniques for representing a native function using an executable reference are disclosed. The system receives an instruction to create an executable reference for a native function, including a method type comprising a method signature corresponding to the executable reference, and a function description including (a) a memory layout corresponding to data returned by the function and (b) memory layouts corresponding to parameters required by the function. The system selects an application binary interface (ABI). The system generates code that, for each parameter, of the one or more parameters required by the function, converts the parameter from a value formatted for use by a Java Virtual machine to a value formatted for use in the native function, based on the selected ABI. Responsive to invocation of the executable reference, the generated code and the native function may be executed.

A build process for building software in a target environment can be generated using a system described herein. For example, the system can receive a recommended software-stack for a target software item to be built in a target build environment. The system can determine, based on the recommended software-stack, a build process for building the target software item in the target build environment. The system may then execute the build process to generate a software build of the target software item in the target build environment.

The invention relates to distributed ledger technologies such as consensus-based blockchains. Computer-implemented N methods for reducing arithmetic circuits derived from smart contracts are described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a programmatic set of conditions encoded in a second programming language. The programmatic set of conditions is precompiled into precompiled program code. The precompiled program code is transformed into an arithmetic circuit. The arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.

Systems, methods, and storage media for creating an interface between a smart contract to be executed on a decentralized architecture and a user component, the method comprising: receiving code corresponding to the smart contract at an interface server; the interface server parsing an application binary interface (ABI) corresponding to the smart contract; the interface server constructing an enhanced application binary interface (EABI) based on the ABI; and the interface server creating a REST API interface specific to the smart contract based on the EABI.

A compiler for a gate-based superconducting quantum computer compiles hybrid classical/quantum algorithms for quantum processing cells with different configurations. The compiler inputs the algorithm and outputs code in a target language executable by a quantum processing cell of a quantum processing system that can execute the algorithm. The compiler includes various functionality, such as: parsing, analyzing control flows, addressing, compressing, and translating. The compiler optimizes algorithms in various manners using the functionality. Some optimizations include addressing efficiently, compressing based on simulations, and translating for efficient execution of parametric functions. The compiler may function in the environment of a cloud quantum computing system. The cloud quantum computing system may receive algorithms from remote access nodes for execution on local classical and quantum computing systems.

Test cases written to test a software application can be dynamically distributed among different sets of test cases that can be executed simultaneously in different parallel threads, thereby speeding up testing relative to executing the test cases sequentially in a single thread. To avoid database conflicts that may occur when different test cases in different parallel threads attempt to access the same database simultaneously, testing of the software application can be performed in association with a record-locking database that locks database records individually instead of locking entire database tables or locking data structures that are larger than individual records. Locking individual database records can reduce and/or eliminate the chances that a test case in one parallel thread will be unable to access a record in the database because another test case in another parallel thread is simultaneously accessing the same database.

The present disclosure is directed to systems and methods directed to improving the functions of a vehicle. Systems and methods are provided that provide a custom tool that autogenerates a set of software agents that allows a system to separate processing, transmission and receiving of messages to achieve better synchronization. The disclosure herein also provides a simplified method of key provisioning by designating one client as a server and assigning a symmetric key to every other client permanently provisioned between that client and the server. Systems and method are further provided that predict faults in a vehicle. Systems and methods are also provided that preserve data in the event of a system crash. Systems and methods are also provided in which an operating system of a vehicle detects the presence of a new peripheral and pulls the related interface file for that new peripheral. Further, a data synchronization solution is provided herein which provides optimized levels of synchronization.

A Quantum Instruction Set Architecture (QUASAR) for quantum control processors, and a method which provides an interface for rapid and consistent development for controlling quantum computing systems which have different quantum computer chips and associated low-level control hardware. The method includes compiling a source program; decoding instructions by checking the opcode and determining whether said instruction is a single-qubit gate operation, a two-qubit gate operation, a measurement operation or a timing control operation; determining if each instruction is an immediate or register-based operation; decoding each specific instruction to generate machine code and/or netlists for execution by a quantum control unit configured for controlling a quantum computer chip and its associated low-level control hardware.