Disclosed are systems and methods related to providing for the optimized software implementations of artificial intelligence (“AI”) networks. The system receives operations (“ops”) consisting of a set of instructions to be performed within an AI network. The system then receives microkernels implementing one or more instructions to be performed within the AI network for a specific hardware component. Next, the system generates a kernel for each of the operations. Generating the kernel for each of the operations includes configuring input data to be received from the AI network; detecting a specific hardware component to be used; selecting one or more microkernels to be invoked by the kernel based on the detection of the specific hardware component; and configuring output data to be sent to the AI network as a result of the invocation of the microkernel(s).

A method for executing new instructions includes the following steps: receiving an instruction and determining whether the received instruction is a new instruction. When the received instruction is the new instruction, entering a system management mode, and simulating the execution of the received instruction by executing at least one old instruction in the system management mode.

The present disclosure discloses a neural network processing module, in which a mapping unit is configured to receive an input neuron and a weight, and then process the input neuron and/or the weight to obtain a processed input neuron and a processed weight; and an operation unit is configured to perform an artificial neural network operation on the processed input neuron and the processed weight. Examples of the present disclosure may reduce additional overhead of the device, reduce the amount of access, and improve efficiency of the neural network operation.

This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index. This disclosure improves operating efficiency of subsequent vector instructions when a fault-only-first vector loading instruction is involved in chaining.

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.

A method for executing a binary code including the execution of an indirect load instruction which provokes the reading of a data line associated with an address obtained from the content of a destination register, then the construction of an initialization vector from the content of this data line, then the loading of this constructed initialization vector in a microprocessor, then the execution of an indirect branch instruction which provokes a branch directly to a first encrypted instruction line of a following basic block whose address is obtained from the content of the same destination register, then the decryption of the cryptogram of each encrypted instruction line of the following basic block using the initialization vector loaded in the microprocessor.

A tutorial system presents a tutorial comprising a series of steps for building a computing system and testing successful completion of at least one of the steps. The computing system comprises a programmable controller and at least one hardware component. The tutorial system is coupled to the target computing system via a connection. The tutorial system may present one or more programming steps for the user to enter and load particular programming to the controller. The tutorial system may further present one or more physical steps for the user to physically configure a particular hardware component, such as physically configuring connections or wiring between the particular hardware component and the controller and/or another hardware component of the computing system. The tutorial system directly tests successful completion of a physical step or a programming step through values received from the computing system via the connection.

An instruction execution method suitable for being executed by a processor is provided. The first processor comprises a register alias table (RAT) and a reservation station. The instruction execution method includes: a register alias table receives a first micro-instruction and a second micro-instruction and issues the first micro-instruction and the second micro-instruction to the reservation station; and the reservation station assigns one of a plurality of execution units to execute the first micro-instruction, according to the first specific message of the first micro-instruction; and the reservation station assigns one of the execution units to execute the second micro-instruction, according to the second specific message of the second micro-instruction. When the reservation station determines that the execution units assigned for the first micro-instruction and the second micro-instruction are the same, the reservation station indicates that the second micro-instruction depends on the first micro-instruction.

Methods and systems for managing notifications relating to execution of microservices are described herein. A format of notifications relating to execution of a plurality of microservices may be defined. The format may provide that all notifications generated based on the format comprise code. The code may indicate, for example, an identity of one of a plurality of microservices, a version of the code, an occurrence of an issue in execution of the one of the plurality of microservices, and/or one or more scripts which may be executed to address an issue of the notification. Two or more notifications may be received, and the one or more notifications may be formatted based on the defined format. A third notification may be generated based on a comparison of the two or more notifications. The third notification may be transmitted to a computing device.

A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction; generating an unknown instruction exception when the received instruction is an unknown instruction; in response to the unknown instruction exception, entering a system management mode; and in the system management mode, executing the following steps through a conversion program: determining whether the received instruction is a new instruction; and simulating the execution of the received instruction by executing at least one old instruction when the received instruction is a new instruction.