In one implementation, systems and methods are provided for developing a computer-implemented digital experience application having a first and a second micro-application. Each micro-application includes a front end interface configured to receive and display information. The first micro-application includes a first event manager configured to detect an application event belonging to a category, and a first state manager configured to detect an application state belonging to the category. The digital experience application further includes a driver application configured to host the first and second micro-applications, an event hub configured to receive the detected application event from the first micro-application, and a state store configured to store the detected application state received from the first micro-application. The second micro-application includes a second event manager configured to receive the detected application event from the event hub, and a second state manager configured to receive the detected application state from the state store.

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for: storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for: storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

The present disclosure discloses a startup method and a wireless handheld device. The present disclosure relates to the field of communications technologies. The startup method includes: when a wireless handheld device is started, if it is detected that a K.sup.th Android installation package file in a data application directory is undergoing installation or updating, decompressing a library file of the K.sup.th Android installation package file to a preset subdirectory in the data application directory, where K is an integer greater than zero. A corresponding wireless handheld device is further provided. By adopting the present disclosure, a startup speed of the wireless handheld device can be improved.

A data storage device includes: a storage configured to store flag information on attributes, each attribute corresponding to a revision version, and firmware comprising register setting information and firmware execution code branch information for each attribute; and a controller configured to read the flag information and the firmware from the storage to execute the firmware according to the flag information.

A data storage device includes: a storage configured to store flag information on attributes, each attribute corresponding to a revision version, and firmware comprising register setting information and firmware execution code branch information for each attribute; and a controller configured to read the flag information and the firmware from the storage to execute the firmware according to the flag information.

An information device has a storage medium storing information items which includes a first program provided on a first partition, a second program and data provided on a second partition to restore the first program on the first partition to a predetermined state, a boot block which causes system activation from one of the first partition and the second partition, and an active-partition switching program which indicates, to the boot block, one of the first and second partitions. An input/output system activates the active-partition switching program when a specific operation is performed. The active-partition switching program indicates to the boot block that system activation is to be executed from the second partition.

A software layout system is described herein that speeds up computer system boot time and/or application initialization time by moving constant data and executable code into byte-addressable, persistent random access memory (BPRAM). The system determines which components and aspects of the operating system or application change infrequently. From this information, the system builds a high performance BPRAM cache to provide faster access to these frequently used components, including the kernel. The result is that kernel or application code and data structures have a high performance access and execution time with regard to memory fetches. Thus, the software layout system provides a faster way to prepare operating systems and applications for normal operation and reduces the time spent on initialization.

Embodiments of an invention for protecting a secure boot process against side channel attacks are disclosed. In one embodiment, an apparatus includes cryptography hardware, a non-volatile memory, a comparator, and control logic. The cryptography hardware is to operate during a first boot process. The non-volatile memory includes a storage location in which to store a count of tampered boots. The comparator is to perform a comparison of the count of tampered boots to a limit. The control logic is to, based on the first comparison, transfer control of the apparatus from the first boot process to a second boot process.

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for: storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.