Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for: storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

An instruction writing method, apparatus, and network device are provided to reduce a requirement for a storage space of a microcode processor. The method includes obtaining, by a first device, first indication information, where the first indication information indicates the first device to enable a first service function, and writing, by the first device, a first microcode instruction set corresponding to the first service function into an unused storage space of a target microcode processor in a network processor, where a size of the unused storage space is greater than or equal to a size of the first microcode instruction set.

An instruction writing method, apparatus, and network device are provided to reduce a requirement for a storage space of a microcode processor. The method includes obtaining, by a first device, first indication information, where the first indication information indicates the first device to enable a first service function, and writing, by the first device, a first microcode instruction set corresponding to the first service function into an unused storage space of a target microcode processor in a network processor, where a size of the unused storage space is greater than or equal to a size of the first microcode instruction set.

A distributed technique for implementing a cryptographic process performs operations in parallel on both valid and irrelevant data to prevent differentiation of the operations based on an encryption key content. A control entity switches or points valid data to appropriate CPU(s) that are responsible for operations such as squaring or multiplying. Irrelevant data is also switched or pointed to appropriate CPU(s) that execute operations in parallel with the CPU(s) operating on the valid data. The distributed technique contributes to obscuring side channel analysis phenomena from observation, such that cryptographic operations cannot easily be tied to the content of the encryption key.

The present invention is notably directed to a user portable device (10), preferably a secure tamper-proof device, comprising: a connection interface (12) enabling connection (S2) with a computer (101); a persistent memory (14); and a bootloader (16) stored on said persistent memory (14), preferably on a secure memory (141) of the device, wherein the bootloader (16): is detectable (S3) by a firmware (122) of the computer (101) upon connection (S2) of the device (10) with said computer (101) via said connection interface; and comprises instructions for said firmware (122) to load (S4) the bootloader (16) into a memory (121) of the computer (101) for subsequent execution (S5); and to interact with the firmware, upon execution at the computer (101), to: determine, in a physical storage medium (120) of said computer (101) storing a first host operating system (111-1) and a second host operating system (111-2) respectively on a first portion (120-1) and a second portion (120-2) thereof, said second portion (120-2), from partition information (111-1p) of said physical storage medium, which partition information acknowledges the first host operating system but does not acknowledge the second host operating system; locate a part (BI) of the second host operating system (111-2) in the second portion (120-2); and execute said part (BI), whereby only the second one of the host operating systems can boot (S6-S8) from the user portable device (10). The present invention is further directed to related systems and methods.

A system and method for effecting a multiple-arm wager incorporating a plurality of events, such as sporting events, includes accessing a wagering system of the type including a central computer accessible by at least one network terminal interconnected thereto and hosting an executable instruction set for computing intermediate revised odds between a minimum and a maximum as a function of bettor-selected point shades to modify the line applicable to selected individual competing event teams for determining whether the selected teams have won the games for purposes of the wager. The line for each team is individually selectively point-shaded in accordance with the wishes of the bettor, and the betting odds for the wager are calculated as a function of the total number of points shaded for the selected teams.

A server computer includes an SDRAM and a service processor that transmits a boot firmware program. The server computer further also includes a CPU that includes a cache for the boot firmware program transmitted from the service processor to be stored in. The CPU executes the boot firmware program stored in the cache to activate the SDRAM, and performs a startup of the server computer by using the activated SDRAM.

A method for synchronizing a casino game playable at a plurality of gaming devices is provided. The method includes receiving, by a server having at least one processor, an indication of a wager from at least one of the plurality of gaming devices, determining, by the server, a schedule for at least one jackpot of the casino game based at least in part on the received indication of the wager, and sending, by the server, the schedule for the at least one jackpot of the casino game to at least a first gaming device and a second gaming device, the sending including sending the schedule to the first gaming device through wired communication channels, and sending the schedule to the second gaming device through at least one wireless communication channel.

An enterprise management system is described for efficient operating system migration, preserving applications, data, and settings. A staging area, such as an empty folder, is created on a client device. A base layer for the new operating system and application layers for applications that will be installed on the computing device are downloaded to the staging area. After the base layer and application layers are downloaded, the layers are merged onto the computing device to instantly install the operating system and the applications. User settings, data, and other applications can be migrated to corresponding locations in the new operating system from the old operating system.

A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.