A processor includes: at least one operator; and at least one macro instruction processing unit configured to share the at least one operator, wherein the at least one macro instruction processing unit is configured to execute a macro instruction with respect to input data by using the at least one operator to output result data, and to control the at least one operator to perform an operation included in the macro instruction, and the at least one macro instruction processing unit comprises: a scheduler configured to manage schedules of the at least one operator and output input data and a control signal to the at least one operator; and a controller configured to control the scheduler to execute the macro instruction and to receive the result data from the scheduler.

An RISC-V-based 3D interconnected multi-core processor architecture and a working method thereof. The RISC-V-based 3D interconnected multi-core processor architecture includes a main control layer, a micro core array layer and an accelerator layer, wherein the main control layer includes a plurality of main cores which are RISC-V instruction set CPU cores, the micro core array layer includes a plurality of micro unit groups including a micro core, a data storage unit, an instruction storage unit and a linking controller, wherein the micro core is an RISC-V instruction set CPU core that executes partial functions of the main core; the accelerator layer is configured to optimize a running speed of space utilization for accelerators meeting specific requirements, wherein some main cores in the main control layer perform data interaction with the accelerator layer, the other main cores interact with the micro core array layer.

Systems and methods for code caching are provided. A first indication of primary source code awaiting execution is received. A resource cache is checked for cached data corresponding to the primary source code. Upon a cache miss in the resource cache, a first executable code compiled from the primary source code is obtained. A secondary source code referenced in the primary source code is selected. A second executable code compiled from the selected secondary source code is obtained. The first executable code and the second executable code are serialized into serialized code. The serialized code is stored as cached data in the resource cache.

Apparatus and methods are disclosed for implementing block-based processors having custom function blocks, including field-programmable gate array (FPGA) implementations. In some examples of the disclosed technology, a dynamically configurable scheduler is configured to issue at least one block-based processor instruction. A custom function block is configured to receive input operands for the instruction and generate ready state data indicating completion of a computation performed for the instruction by the respective custom function block.

A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.

A method of performing out-of-order execution in a processing system comprising a processing unit and one or more accelerators comprises dispatching a plurality of coarse-grained instructions, each instruction extended to comprise one or more tags, wherein each tag comprises dependency information for the respective instruction expressed at a coarse-grained level. The method also comprises translating the plurality of coarse-grained instructions into a plurality of fine-grained instructions, wherein the dependency information is translated into dependencies expressed at a fine-grained level. Further, the method comprises resolving the dependencies at the fine-grained level and scheduling the plurality of fine-grained instructions for execution across the one or more accelerators in the processing system.

Methods, apparatuses, systems, and implementations of a zero silent data corruption (ZDC) compiler technique are disclosed. The ZDC technique may use an effective instruction duplication approach to protect programs from soft errors. The ZDC may also provide an effective control flow checking mechanism to detect most control flow errors. The ZDC technique may provide a failure percentage close to zero while incurring a lower performance overhead than prior art systems. The ZDC may also be effectively applied in a multi-thread environment.

A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction, wherein the instruction is an unknown instruction; determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction.