Patent classifications
G06F9/461
COOPERATIVE GARBAGE COLLECTION BARRIER ELISION
Techniques are disclosed for eliding load and store barriers while maintaining garbage collection invariants. Embodiments described herein include techniques for identifying an instruction, such as a safepoint poll, that checks whether to pause a thread between execution of a dominant and dominated access to the same data field. If a poll instruction is identified between the two data accesses, then a pointer for the data field may be recorded in an entry associated with the poll instruction. When the thread is paused to execute a garbage collection operation, the recorded information may be used to update values associated with the data field in memory such that the dominated access may be executed without any load or store barriers.
AGGREGATING BLOCK MAPPING METADATA TO IMPROVE LINKED CLONE READ PERFORMANCE
Linked clone read performance (e.g., retrieving data) is improved at least by minimizing the number of input/output (I/O) operations. For a child clone, a local logical extent and an inherited logical extent are generated. The local logical extent comprises a logical block address (LBA) for data in a data region of the child clone and a physical sector address (PSA) corresponding to the LBA for the data in the data region of the child clone. The inherited logical extent spans logical extents that are accessible to the child clone. The inherited logical extent comprises an LBA for data in a data region of an ancestor of the child clone and a corresponding identifier (ID) of the ancestor. Data for an LBA in a read request may be rapidly found in the child clone (local logical extent) or an ancestor (inherited logical extent).
Database recovery time objective optimization with synthetic snapshots
Methods and systems for reducing the amount of time to restore a database or other application by dynamically generating and storing synthetic snapshots are described. When backing up a database, an integrated data management and storage system may acquire snapshots of the database at a snapshot frequency and acquire database transaction logs at a frequency that is greater than the snapshot frequency. In response to detecting that the database is unable to provide a database snapshot, the integrated data management and storage system may generate a synthetic snapshot of the database by instantiating a compatible version of the database locally, acquiring a previously stored snapshot of the database, applying data changes from one or more database transaction logs to the previously stored snapshot to generate the synthetic snapshot, and storing the synthetic snapshot of the database within the integrated data management and storage system.
INCREMENTAL RESTORE OF A VIRTUAL MACHINE
Techniques are provided for incrementally restoring a virtual machine hosted by a computing environment. In response to receiving an indication that the virtual machine is to be incrementally restored, a snapshot of the virtual machine may be created while the virtual machine is shut down into an off state. The snapshot is transmitted to a storage environment as a common snapshot. The snapshot and the common snapshot are common snapshots comprising a same representation of the virtual machine. The common snapshot and a prior snapshot of the virtual machine are evaluated to identify a data difference of the virtual machine between the common snapshot and the prior snapshot. An incremental restore is performed of the virtual machine by transmitting the data difference from the storage environment to the computing environment to restore the virtual machine to a state represented by the prior snapshot.
Marking current context data to control a context-data-dependent processing operation to save current or default context data to a data location
A data processing system includes processing circuitry for executing context-data-dependent program instructions which are decoded by decoder circuitry. Such context-data-dependent program instructions perform processing which is dependent upon currently existing context data. As an example, the context-data-dependent program instructions may be floating point instructions and the context data may be rounding mode information. The decoder circuitry supports a context save instruction which saves context data when it is marked as having been used and saves default context data when the current context data is marked as not having been used. The decoder circuitry further supports a context restore instruction which restores context data when the current context data is marked as having been used and permits the current context data to continue for future use when it is marked as currently unused.
HITLESS CONTAINER UPGRADE WITHOUT AN ORCHESTRATOR
Systems, methods, and computer-readable media are disclosed for performing a hitless upgrade of executable code in the absence of an orchestrator or other upgrade manager. A mechanism is disclosed that utilizes containers to update software functionality, features, or the like without interrupting a service provided by a container and without relying on an orchestrator or other upgrade manager to coordinate the upgrade process. State information indicative of a current state of module(s) within a container is maintained in an external data store such as a state database. A hand-off from a current container to a new container that updates module code/functionality of the current container can be initiated upon determining that a state metric calculated by the old container at a future timestamp matches a state metric independently calculated by the new container at the same timestamp.
Serverless Application Function Execution
Executing serverless application functions is provided. A response to a user request for a service is received with an include callback parameter and a transaction identifier of the user request included in a header of the response from an external service via a network. A checkpoint of a container corresponding to the service is retrieved from a data store using the transaction identifier of the user request. The container corresponding to the service is restored using the checkpoint to process the response received from the external service.
Compiler-optimized context switching with compiler-inserted data table for in-use register identification at a preferred preemption point
Compiler-optimized context switching may include receiving an instruction indicating a preferred preemption point comprising an instruction address; storing the preferred preemption point in a data structure; determining, based on the data structure, that the preferred preemption point has been reached by a first thread; determining that preemption of the first thread for a second thread has been requested; and performing a context switch to the second thread.
Data storage apparatus including swap memory and operating method thereof
A data storage apparatus includes a storage device; a controller to control data input and output operations of the storage device; and a swap memory provided in an outside of the controller, wherein the controller includes a thread manager to perform a preparation operation on a first thread included in a task in response to a request for processing the task, request the storage device to process the first thread on which the preparation operation has been performed, perform a preparation operation on at least one subsequent thread following the first thread while the storage device processes the first thread, and store context data of the first thread and the at least one subsequent thread in the swap memory, wherein the task includes the first thread and the at least one subsequent thread, and the preparation operation includes an address mapping operation.
Monolithic vector processor configured to operate on variable length vectors using a vector length register
A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.