A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.

An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

A monitoring method includes: performing, by a first arithmetic and logic unit of an electronic circuit unit, a first processing rule to obtain a first processing result, performing, by a second arithmetic and logic unit of an electronic circuit unit, a second processing rule to obtain a second processing result, and, using a protection module of a safety area of the electronic circuit unit, identifying an error-free state of the electronic circuit unit in response to the first and second results having a predefined relationship to each other and/or the first and second results having a predefined relationship to a predefined criterion, where the protection module is configured to ensure that algorithms are carried out in a manner that is better protected from an incorrect execution than the first and second arithmetic and logic units.

According to one embodiment, the first processing unit receives a first clock and outputs, at its first output node, data obtained by first processing of data at an input node. The second processing unit receives a first clock and outputs, at its second output node, data obtained by the first processing of the data at the input node. The third processing receives a second clock, outputs, from its third output nodes, data obtained by the first processing of the data at the input node, and outputs, from its fourth output nodes, data obtained by the first processing of the data at the input node. The determination unit outputs a first signal based on data at the fifth to eighth nodes respectively coupled to the first to fourth output nodes.

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

A monitoring method includes: performing, by a first arithmetic and logic unit of an electronic circuit unit, a first processing rule to obtain a first processing result, performing, by a second arithmetic and logic unit of an electronic circuit unit, a second processing rule to obtain a second processing result, and, using a protection module of a safety area of the electronic circuit unit, identifying an error-free state of the electronic circuit unit in response to the first and second results having a predefined relationship to each other and/or the first and second results having a predefined relationship to a predefined criterion, where the protection module is configured to ensure that algorithms are carried out in a manner that is better protected from an incorrect execution than the first and second arithmetic and logic units.

A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Camera heads and associated systems, methods, and devices for inspecting and/or mapping pipes or cavities are disclosed. A camera head may be coupled to a push-cable and may include one or more image sensors to capture images and/or videos from interior of the pipe or cavity. One or more multi-axis sensors may be disposed in the camera head to sense data corresponding to movement of the camera head within the pipe or cavity. The images and/or videos captured by the image sensors may be used in conjunction with the data sensed by the multi-axis sensors to generate information pertaining to the pipe or cavity may be generated.

Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.

A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects