In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

A serial interface, such as a serial peripheral interface (SPI), with improved diagnostic coverage is disclosed. The serial interface includes a data verification module that selects an error detection value in response to a mode signal indicating if the transmitting device is in user mode or test mode. For example, the data verification module computes a cyclic redundancy check (CRC) value and selects either the computed CRC value or its inverse based on the mode. The receiving device can determine the mode of the transmitting device based on the error detection value used. The serial interface further includes a read detector for clearing the transmit data buffer after data is read out. The serial interface may further include a loopback circuit for verifying that the data output from an output pin matches the data from the transmit data buffer.

It is possible to intuitively identify the reason for the handshake failure. An entire state transition flow including each state based on the communication standard and a state transition condition to be executed between states is displayed as a state transition setting screen 11, and an immediately preceding state in which the state transition fails and the failed state transition condition are highlighted on the state transition setting screen 11, when the handshake with the device under test ends.

A test apparatus is provided for use with a mainframe and an adapter. The test apparatus includes a logical adapter interface unit and a control system. The logical adapter interface unit is interposable between the adapter and the mainframe whereby an I/O signal transmittable from the adapter and to the mainframe is transmitted through the logical adapter interface unit. The logical adapter interface unit is configured to manipulate the I/O signal. The control system is coupled to the logical adapter interface unit and the mainframe and is configured to control manipulations of the I/O signal by the logical adapter interface unit to mimic a condition of I/O traffic being run through the adapter and to log a response of the mainframe to the manipulations.

A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

The state transition condition can be adjusted flexibly and easily while taking advantage of the handshake-type technique. A state transition setting screen 11 of an entire state transition flow including a name 12 of each state based on a communication standard and a state transition condition 13 to be executed between states is displayed on a display screen 6a, and input setting for the state transition condition is possible on the state transition setting screen 11.

A modular system is described which can provide high frequency monitoring of power use and responsive control as well as enabling network connectivity for centralised monitoring and operation. One modular system consists of a communications bus, end caps, and a combination of the modules providing communications, power metering, relay control and battery backup. Each modular system can be configured with a combination of modular units as needed for the application. A combination of bus communication monitoring and tilt detection provides security against external tampering after installation.

An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.