Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

An apparatus to initialize a port includes a first input-output port to connect to a first device and, a control unit to initialize all input-output ports of the apparatus when the apparatus is booted and to skip a power-on self-test (POST) of the first input-output port in response to a request to skip initialization of the first input-output port while the first input-output port is enabled.

Aspects of the embodiments are directed to systems, methods, and apparatuses to determine transmission equalization coefficients (TxEQs) for one or more lanes of a high speed serial link. Embodiments include determining a jitter tolerance for each TxEQ of a plurality of TxEQs for a lane of the link. The jitter tolerance for each TxEQ for the lane is based on a level of jitter induced on the lane to detect a number of errors on the lane; determining a voltage (VOC) margin for each TxEQ for the lane, wherein the voltage margin for the lane is based on a voltage corners test applied to the lane to detect a number of errors on the lane at a high voltage point and a low voltage point; determining a TxEQ that provides maximum jitter tolerance and based on the determined lowest voltage margin; and using the TxEQ for the lane during operation.

An apparatus is for testing a device to be supplied with power via USB Power Delivery (USB-PD). The apparatus includes at least one USB Type-C connector configured to be connected to the device to be supplied with power to be tested, the at least one USB Type-C connector including a power supply terminal. Processing circuitry of the apparatus is configured to verify that a voltage at the power supply terminal is lower than a first threshold, verify a role of the device, generate requests representative of power supply configurations supported by the role of the device, and verify compatibility of the power supply configurations supported by the device with standardized power supply configurations.

A computing system initialization system includes a BIOS processing system coupled to a computing device via a first I/O access connection, to a BIOS memory system via a second I/O access connection that is a relatively higher speed I/O access connection than the first I/O connection, and to a BIOS module. The BIOS processing system retrieves device data from the computing device via the first I/O access connection, stores the device data in the BIOS memory system via the second I/O access connection, and performs initialization operations subsequent to storing the device data in the BIOS memory system. During the initialization operations, the BIOS processing determines that the BIOS module requires the device data and, in response, retrieves the device data from the BIOS memory system via the second I/O access connection, and provides the device data that was retrieved from the BIOS memory system to the BIOS module.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.

A USB integrated circuit (IC), a testing platform and an operating method for USB integrated circuit are provided. The USB integrated circuit includes a USB port physical layer (PHY) circuit, a first lane adapter, a second lane adapter, a routing circuit, and a USB transport layer circuit. The USB PHY circuit is configured to transmit a differential signal between the USB integrated circuit and an outside device. When the USB integrated circuit operates in a testing mode, the routing circuit electrically connects the first lane adapter to the USB PHY circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second lane adapter to the USB PHY circuit. The USB transport layer circuit is coupled to the first lane adapter and the second lane adapter.