A bus system for a process system, having a first bus subscriber which transmits bus messages and having at least one first bus subscriber which receives bus messages, wherein the transmitting first bus subscriber and the receiving first bus subscriber are connected to one another via a first data bus, wherein the transmitting first bus subscriber is designed such that it transmits control commands to the receiving first bus subscriber, wherein the receiving first bus subscriber is designed such that it executes the control commands of the transmitting first bus subscriber and achieves the object of providing a bus system that is designed to be fail-safe in a special way.

A link downgrade detection system includes an interface that is coupled to an endpoint device. The endpoint device is configured to provide an endpoint link that includes a first link capability at a maximum first link capability level and a second link capability at a maximum second link capability level. The endpoint device stores a working first link capability level and a working second link capability level in a first memory device included on the endpoint device. A BIOS coupled to the chassis interface enumerates the endpoint device, determines an actual first link capability level and an actual second link capability level, and retrieves the working link capability levels. The BIOS then determines, based on the working link capability levels and the actual link capability levels that the endpoint link is downgraded, and in response provides a notification that the endpoint link of the endpoint device is downgraded.

This disclosure concerns a medical device designed for delivering a medical fluid or designed for controlling delivery of a medical fluid, and to a method of operating such a medical device. The medical device comprises a user interface associated with an electronic circuit connected to a first port and to a second port of a controller. The electronic circuit enables the controller to detect actuation of the user interface. The controller is configured to execute the following sequence of steps: first step: configure the first port as an output port and to apply a first signal to the first port; second step: to acquire a second signal from the second port; and third step: to determine on the basis of the second signal if a short circuit has occurred and to generate a short circuit alert signal if applicable.

Techniques for error detection involve injecting, to a switch of a storage system, information representing an error of at least one device to be tested of the system, such that the information representing the error is passed from an upstream port of the switch to a computing device connected with the switch, the switch being connected to the at least one device to be tested via a downstream port. The techniques further involve obtaining a handling result of the computing device on the information representing the error, and determining an error handling capability of the system at least partly by analyzing the handling result. Accordingly, slave storage devices of storage system nodes, connectors, the entire PCIe topology at the CPU level, and an NVMe bus can be tested, so that the entire logical path of the error handling can be tested, thereby improving performance and saving testing costs.

A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.

It is an object of the present invention to provide a debug system that accesses a semiconductor apparatus from the outside by a simple configuration at less overhead. The present invention relates to a semiconductor apparatus and a debug system. A large scale integration (LSI 11) includes a central processing unit (CPU 20), a debug control portion (21), an internal bus (22), a storage portion (23, 24, 26) connected to the internal bus, and a selector (27). According to a select control signal (CNT) from the CPU, the selector selects either a CPU select state of transmitting a signal from the CPU to the internal bus, or a debugger select state of transmitting a signal from the debug control portion to the internal bus. In principle, the selector is set to the CPU select state. Upon receiving a predetermined command from an external device (12, 13) by the debug control portion, a signal corresponding to the predetermined command is sent from the debug control portion to the CPU, and the selector is temporarily set to the debugger select state, thereby accessing the internal bus through the debug control portion.

A system level error detection and handling of the network IO in a multi-chip-package (MCP) die is provided. The error detection and handling mechanism conceived may be used between a system-on-chip (SoC) die and a different type of die, such as a die manufactured by a third-party (e.g., a high-bandwidth network IO die). To provide a timely indication in case of any part of the network is at fault, a control unit on the SoC die handles error detection on the network IO links using various indicators. After errors are detected, the control unit groups the errors into two categories: a link failure and a virtual channel failure. Such an error handling mechanism may consolidate the actions and provide consistency in hardware behavior.

Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.

Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

A modular system is described which can provide high frequency monitoring of power use and responsive control as well as enabling network connectivity for centralised monitoring and operation. One modular system consists of a communications bus, end caps, and a combination of the modules providing communications, power metering, relay control and battery backup. Each modular system can be configured with a combination of modular units as needed for the application. A combination of bus communication monitoring and tilt detection provides security against external tampering after installation.