Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.

Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

An electronic device includes a syndrome decoder, an error insertion control circuit, and a failure detection circuit. The syndrome decoder generates an error insertion code from a write syndrome generated based on a write pulse. The error insertion control circuit inserts an error into an internal codeword according to the error insertion code based on a read pulse. The failure detection circuit compares the write syndrome with a read syndrome generated from the internal codeword to generate a failure detection signal.

A Recovery Maturity Index 1 (RMM) is used to determine whether a particular Information Technology (IT) production environment is relatively mature enough to successfully execute the disaster recovery (DR). The RMI provides a quantitative analysis in terms of a set of categories for elements that characterize the environment and multiple elements for each category. At least some of the elements depend upon the extent to which automation components have been leveraged for disaster recovery. A summation of the scoring elements, which may be a weighted summation, results in an overall quantitative metric. The metric can used to determine whether or not disaster recovery can be expected to be successful.

A compliance user or auditor is enabled to inject failures into a sandbox environment, which may be similar to a production service. The sandbox environment may be monitored by the same automation that watches compliance controls in the production service. As the user injects compliance failures into the sandbox, they may detect the appropriate alerts fire in the monitoring system, thereby gaining trust that the monitoring works as it should. A rich report resulting from the test activities may allow the user or auditor to see how a failure of a compliance control leads to the expected monitoring alert.

An electronic control unit includes a computer that outputs a monitoring signal and an external monitoring circuit that monitors a state of the computer based on the monitoring signal. The computer includes a monitoring signal output section that generates and outputs the monitoring signal to the external monitoring circuit by performing a software process; a self-diagnostic section that self-diagnoses the computer and detects an abnormality by identifying a cause of the abnormality; and a break signal output section that outputs a break signal to interrupt an input of the monitoring signal to the external monitoring circuit by performing a hardware process when an abnormality in the monitoring signal output section is detected.

A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor device 1 has a plurality of hierarchical modules and an error control module 100 for controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control module 100 includes a status register 120 configured to record data indicative of the status of failure of each hierarchical module, and a fault injection function 110 that outputs an error signal to the status register 120 to perform fault injection test. The error signal is inputted into the safety mechanism via the status register 120.

A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.

A method of performing a built in test on a watchdog circuit including a watchdog timer includes: initiating the built in test with a processor being monitored by the watchdog circuit, wherein initiating includes enabling a watchdog circuit built in test reset inhibit circuit (WD BIT reset inhibit circuit) connected between an output of an active watchdog integrated reset circuit connected to the processor and a reset input of the processor; and ceasing to provide a strobe signal to the active watchdog integrated reset circuit that resets a watchdog counter in the active watchdog integrated reset circuit, the active watchdog integrated reset circuit causing a reset of the processor via its output when the watchdog counter expires by providing a signal to a reset input of the processor.