An electronic device includes a syndrome decoder, an error insertion control circuit, and a failure detection circuit. The syndrome decoder generates an error insertion code from a write syndrome generated based on a write pulse. The error insertion control circuit inserts an error into an internal codeword according to the error insertion code based on a read pulse. The failure detection circuit compares the write syndrome with a read syndrome generated from the internal codeword to generate a failure detection signal.

A system and a method for error-correction code (ECC) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.

A system for configuring an intrusion detection system. The system includes an input device, a display device, and an electronic processor. The electronic processor is configured to receive input, via the input device. The input the electronic processor receives includes a previous configuration file, a databus configuration file, and user input. The electronic processor is also configured to run, with an intrusion detection system configuration tool, a simulation of communication on a vehicle communication system based on the input received and display, on the display device, results of running the simulation with the intrusion detection system configuration tool. The electronic processor is further configured to output a new configuration file and a file configured to be uploaded to a vehicle.

Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.

An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.

An electronic device may include a data conversion circuit, a parity conversion circuit and a verification signal generation circuit. The data conversion circuit may be configured to convert the data to generate internal data. The parity conversion circuit may be configured to convert a parity to generate an internal parity. The verification signal generation circuit may be configured to generate a verification signal from a syndrome signal and the error insertion code. The syndrome signal may be generated from the internal data and the internal parity.

A self-test method of a flash memory device includes: generating input data; encoding the input data to generate an error correction code; utilizing the input data and the error correction code to simulate to read a page of a flash memory of the flash memory device to generate soft information; and decoding the soft information to generate a decoding result.

A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.