A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

A compliance user or auditor is enabled to inject failures into a sandbox environment, which may be similar to a production service. The sandbox environment may be monitored by the same automation that watches compliance controls in the production service. As the user injects compliance failures into the sandbox, they may detect the appropriate alerts fire in the monitoring system, thereby gaining trust that the monitoring works as it should. A rich report resulting from the test activities may allow the user or auditor to see how a failure of a compliance control leads to the expected monitoring alert.

Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.

A computer system is provided that includes a cloud platform that includes a plurality of nodes. Each node includes a processor configured to run virtual machines. The cloud platform includes a fault condition injection engine configured to generate fault conditions on selected nodes of the plurality of nodes. The computer system further includes a user interface system configured to receive user input of fault condition experimentation parameters from a user for a target virtual machine associated with the user. The cloud platform allocates a set of nodes of the plurality of nodes for a controlled sandbox environment configured to run the target virtual machine of the user. The fault condition injection engine generates fault conditions on the allocated set of nodes based on the fault condition experimentation parameters.

A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.

An information processing includes a processor and monitors a plurality of operational servers to which processing is allocated. The processor determines an operational server on which failover will be performed in a failover test from among the plurality of operational servers in accordance with a number of the plurality of operational servers and a load, when a condition under which the failover test is conducted is satisfied, and issues a request to measure a failover time of the failover test that is conducted on the determined operational server.

Systems and methods for automated integration and stress testing of hardware and software services in a management controller using a containerized toolbox. The method utilizes a containerized toolbox module, which includes multiple testing tools for a web-based protocol, such as a Representational State Transfer (REST) protocol, and an Intelligent Platform Management Interface (IPMI) protocol. A management controller to be tested by the containerized toolbox module provides multiple services accessible under the web-based protocol and the IPMI protocol. In operation, the containerized toolbox module is provided at the management controller, and receives a testing command to perform a plurality of tests to the services of the management controller. Based on the testing command, the containerized toolbox module performs the tests to the services of the management controller using the testing tools of the containerized toolbox module.

In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.

An electronic control unit includes a computer that outputs a monitoring signal and an external monitoring circuit that monitors a state of the computer based on the monitoring signal. The computer includes a monitoring signal output section that generates and outputs the monitoring signal to the external monitoring circuit by performing a software process; a self-diagnostic section that self-diagnoses the computer and detects an abnormality by identifying a cause of the abnormality; and a break signal output section that outputs a break signal to interrupt an input of the monitoring signal to the external monitoring circuit by performing a hardware process when an abnormality in the monitoring signal output section is detected.

Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized informatione.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.