During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

A device, such as a system on a chip (SoC), includes a plurality of processor cores, a broadcaster module, a plurality of decoder units, and an aggregator module. The broadcaster module broadcasts a debug request from a debugger device to one or more of the plurality of processor cores via a bus, the debug request including an address specifying a logical identifier associated with a target processor core of the plurality of processor cores. The decoder units, associated with the processor cores, forward the debug request to a debug module of the respective processor core in response to detecting a match. If no match is detected, the decoder units forward the debug request to a subsequent processor core via the bus. The aggregator module forward a response message to the debugger device, the response message originating from the target processor core.

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

Methods are provided for supervising a motor control unit with at least two separate channels, each of the two channels including at least: means for executing a given application task AS, the application task AS including a plurality of successively executed computations between which latency periods elapse; a first component capable of performing the computations; a second component capable of storing data; the application tasks AS of the channels being capable of communicating. The method comprising includes the following steps: a) detecting a latency period; b) performing, during this latency period, an operating state test of at least one of the components; and c) determining a state of the component corresponding to a failure state or a healthy state.

A method for repairing a processor. The processor comprises a plurality of processing units and an exchange comprising a plurality of exchange paths for transmitting data between the processing units. Each processing unit is connected to output data to a respective exchange path. An exchange path functional test of at least a portion of the exchange paths is carried out. Based on the exchange path functional test, it is identified that one or more of the exchange paths is defective, and the processing units connected to the one or more defective exchange paths is identified. The identified processing units are switched out of functional operation of the processor and switching in at least one repair processing unit connected to a non-defective exchange path for functional operation of the processor.

A processor comprises an exchange, a plurality of columns, and a plurality of exchange scan chains. The exchange comprises a plurality of exchange paths, each comprising a set of exchange path portions, for transmitting data between processing units. Each of the plurality of column comprises processing units, each processing unit connected to output data to a respective exchange path, and column pipe circuitry for providing a controllable path between the exchange and the processing units. The column pipe circuitry comprises a column wrapper chain for preventing a scan test signal from passing between the exchange paths and the processing units. The exchange scan chains enable scan testing of the exchange paths. Each exchange scan chain comprises a plurality of scan chain segments, each scan chain segment comprises an exchange path portion connected to at least one of the processing units of at least one of the columns of the processor.

An automatic processing system, a system on chip and a method for monitoring a processing module are described herein. The automatic driving processing system comprises: an automatic driving processing module, configured for receiving an input data stream and processing the input data stream based on a deep learning model so as to generate a processing result; a fault detection module, configured for generating a control signal and a fault detection stimulating data stream, and receiving the processing result from the automatic driving processing module; and a multi-way selection module, configured for receiving an automatic driving data stream as well as the control signal and the fault detection stimulating data stream, and selectively outputting the automatic driving data stream or the fault detection stimulating data stream to the automatic driving processing module based on the control signal, as an input data stream.

A system for testing a design of a computing component includes an input device configured to receive a request to perform a test of a component, and a testing unit including a simulation of the component. The simulation is configured to output a result indicative of a response to a set of instruction addresses, the set of instruction addresses is acquired from a plurality of addresses, and the plurality of addresses including a plurality of address groups, where each address group is associated with a respective group identifier. The system also includes a plurality of requestors configured to apply the set of instruction addresses to the simulation, where a requestor of the plurality of requestors is configured to select an address for application to the simulation based on a received group identifier and a variably configurable weight value assigned to the received group identifier and the requestor.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.