An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, and a plurality of PLL-timed physical devices that are identical to the physical devices used in the customer's communication system. A first connector receptacle and a second connector receptacle are coupled to the control logic and to one or more of the PLL-timed physical devices, and are configured to receive a PLL card including a PLL timing device. A third connector receptacle is coupled in series between the first connector receptacle and the second connector receptacle and is configured to receive a backplane emulator card having electrical characteristics emulating a backplane of the customer's communication system.

An integrated vehicle health management (IVHM) system to resolve equipment-fault related anomalies detected by cyber intrusion detection system (IDS). A benefit of the present system is that it can result in fewer alerts that need manual analysis. A combination of cyber and monitoring with integrated vehicle health management (IVHM) may be a high value differentiator. As a solution gets more mature through a learning loop, it may be customized for different customers in a cost-effective manner, something that might be expensive to develop on their own for most original equipment manufacturers (OEMs). An IVHM symptom pattern recognition matrix may link a pattern of reported symptoms to known equipment failures. This matrix may be initialized from the vehicle design data but its entries may get updated by a learning loop that improves a correlation by incorporating results of investigations.

Disclosed are hardware and techniques for testing computer processes in a network system by simulating computer process faults and identifying risk associated with correcting the simulated fault and identifying computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a risk matrix having a risk score and non-functional requirement score. An analysis of the risk score and non-functional requirement score accounts for interdependencies between computer processes and identified corrective actions that may be used to determine an optimal network environment. The optimal network environment may be updated dynamically based on changing computer process interdependencies and the determined risk and robustness scores.

A system configured to perform a digital simulation of a hardware device, where the hardware device has a digital state component. The system creates an instance of a first module inside a target module associated with the state component, where the source code of the target module remains unmodified by the instance. The system then resets the simulation, such that the state component is set to one of a fixed state and an unknown state, where the unknown state indicates the digital simulation cannot predict how silicon on the hardware device will behave. The system reads an updated value of the digital state component via the instance of the first module, compares the updated value of the digital state component to a desired value of the digital state component, and generates an alert that the updated value does not match the desired value according to the comparison.

A testing device for real-time testing of at least a part of a virtual electronic control unit with an electronic control unit code is provided. The testing device has a computing unit of a first type, and a computing unit of a second type. The testing of a virtual electronic control unit with electronic control unit code, which is executable on the computing unit of the second type with a second instruction set, is made possible in that a computing unit of the first type executes an emulator for emulating the computing unit of the second type and the emulator executes the electronic control unit code. The emulator also has a simulation environment interface for exchanging data and/or events with the simulation environment.

Systems and methods that enable hardware memory error tolerant software systems. For instance, the system may comprise a host device that instantiates a kernel agent in response to one or more requests to access hardware memory, determines, by the kernel agent based on the received information, whether the request to access memory will cause access to a corrupt memory location, and skip an operation associated with the corrupt memory location in response to determining that the request will access a corrupt memory location. The systems may also include a system that detects software vulnerabilities to hardware memory errors.

A method and system for secure automated deployment of an emulated computer system. The method includes providing a download package for installation on a target machine. The download package includes a generic emulated computer system having no unique identity, no model identity, no features, and minimal processing components. The download package also includes a customer order file based on an order from a customer of the target machine. The customer order file includes a machine identity, at least one machine capability, and control data. The download package also includes at least one enabling key configured to enable the emulated computer system on the target machine. The enabling key is customized based on the order from the customer of the target machine, and includes identity information that restricts the use of the emulated computer system on any computer system other than the target machine. The method also includes delivering the download package to the target machine for installation of the emulated computer system on the target machine. The download package prevents the unauthorized cloning of the emulated computer system onto any hardware platforms other than the target machine, and prevents the unauthorized use of any hardware other than the hardware of the target machine.

A system for testing a design of a computing component includes an input device configured to receive a request to perform a test of a component, and a testing unit including a simulation of the component. The simulation is configured to output a result indicative of a response to a set of instruction addresses, the set of instruction addresses is acquired from a plurality of addresses, and the plurality of addresses including a plurality of address groups, where each address group is associated with a respective group identifier. The system also includes a plurality of requestors configured to apply the set of instruction addresses to the simulation, where a requestor of the plurality of requestors is configured to select an address for application to the simulation based on a received group identifier and a variably configurable weight value assigned to the received group identifier and the requestor.

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Provided method includes storing a first cache snap shot including cache profiling information regarding a cache when a first process being executed by a cycle accurate simulator is terminated; storing a second cache snap shot including the cache profiling information on the cache when a second process is executed in the cycle accurate simulator; comparing the second cache snap shot of the second process and the first cache snap shot of the first process to readjust any one value of a cache hit value and a cache miss value which are present in the second cache snap shot of the second process; and correcting the cache profiling information which is stored in the first cache snap shot of the first process by reflecting the readjusted any one value of the cache hit value and the cache miss value present in the second cache snap shot of the second process.