A programmable testing apparatus imposes power interruptions on a storage device at any given point of time under at least one workload according to at least one protocol for tests. The programmable testing apparatus includes a controller unit connected to a workload unit, a power control unit, a protocol control unit and a data buffer unit. The controller unit calculates and receives and replies commands in the tests. The workload unit imposes various workloads on the storage device. The power control unit imposes power interruptions on the storage device under control of the controller unit. The protocol control unit provides commands according to the protocol for tests. The data buffer unit stores critical data and information to check whether data stored in the storage device are correct.

A method for evaluating an electronic design under test may be performed in an environment that includes a functional verification test bench having at least one verification component coupled to the electronic design under test. The method includes provisioning the functional verification test bench to provide protocol-agnostic performance data for activity of the electronic design under test during functional verification testing of the electronic design under test. The method further includes capturing at least a part of the protocol-agnostic performance data from the at least one verification component, and calculating, from the protocol-agnostic performance data, a performance measurement for the electronic design under test.

A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting the list of objects associated with the previous clock cycle with the one or more objects associated with the one or more commands to be executed during the clock cycle. Output values for objects included in the updated list of objects is selected. The filtered test output is then stored in an activity database.

A method, apparatus and a product for utilizing translation tables for testing processors. The method is used for testing a target processor that utilizes different translation tables to translate virtual addresses to physical addresses. The method comprises obtaining a test template that comprises directives to be executed in different contexts, during each of which a different translation table is utilized to translate virtual addresses to physical addresses. The translation tables to be used by the target processor in the different contexts are determined, so that the translation tables overlap, at least in part.

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

Immersive web-based simulator for digital assistant-based applications is provided. A system can provide, for display in a web browser, an inner iframe configured to load, in a secure, access restricted computing environment, an application configured to integrate with a digital assistant. The application can be provided by a third-party developer device. The system can provide, for display in a web browser, an outer iframe configured with a two-way communication protocol to communicate with the inner iframe. The system can provide a state machine to identify a current state of the application loaded in the inner frame, and load a next state of the application responsive to a control input.

A method of testing a physical system that includes software and hardware includes developing a software application arranged to operate at least a portion of the physical system and constructing a simulation of the physical system within a test ecosystem, the simulation including inputs that simulate control inputs of the physical system and outputs that simulate control and informational outputs. The method also includes connecting the software application to the simulation of the physical system to test the operation of the software application, and simulating operation of the physical system and the software application within test ecosystem operation of the software application as each of a cloud application, a network operation of the software application as each of a cloud application, a network application, and a local application.

Disclosed is a quantum diagnostic circuit, which includes an input unit having an input of at least first to fourth qubits, a diagnostic circuit unit receiving the first to fourth qubits from the input unit and providing a quantum superposition and a quantum entanglement, and an output unit receiving an output of the diagnostic circuit unit and determining whether the output is in a Bell-state, and the diagnostic circuit unit includes a Hadamard gate processing the first qubit to provide the quantum superposition of the first to fourth qubits, a first CNOT gate providing the quantum entanglement between an output of the Hadamard gate and the second qubit, a second CNOT gate providing the quantum entanglement between an output of the first CNOT gate and the third qubit, and a third CNOT gate providing the quantum entanglement between an output of the second CNOT gate and the fourth qubit.

A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.

Techniques for testing a physical hardware system by executing hardware system application software on a corresponding emulated proxy physical hardware system in a proxy virtual machine are presented. The techniques include: obtaining a proxy physical hardware system that matches aspects of the physical hardware system; constructing, in a virtualization system, the proxy virtual machine; emulating, using the virtualization system, hardware components of the proxy physical hardware system in the proxy virtual machine; executing a hardware abstraction software layer in the proxy virtual machine; executing, by the hardware abstraction software layer of the virtualization system, the hardware system application software in the proxy virtual machine on the proxy physical hardware system using a memory map at least one adapter; and testing, using the virtualization system, the physical hardware system by the executing the hardware system application software in the proxy virtual machine on the proxy physical hardware system.